Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4199779 [patent_doc_number] => 06021458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method and apparatus for handling multiple level-triggered and edge-triggered interrupts' [patent_app_type] => 1 [patent_app_number] => 9/010226 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5693 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021458.pdf [firstpage_image] =>[orig_patent_app_number] => 010226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010226
Method and apparatus for handling multiple level-triggered and edge-triggered interrupts Jan 20, 1998 Issued
Array ( [id] => 4121857 [patent_doc_number] => 06052753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Fault tolerant data bus' [patent_app_type] => 1 [patent_app_number] => 9/009463 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 21038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052753.pdf [firstpage_image] =>[orig_patent_app_number] => 009463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009463
Fault tolerant data bus Jan 19, 1998 Issued
Array ( [id] => 4177407 [patent_doc_number] => 06108733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method for extending the available number of configuration registers' [patent_app_type] => 1 [patent_app_number] => 9/008966 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2792 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108733.pdf [firstpage_image] =>[orig_patent_app_number] => 008966 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008966
Method for extending the available number of configuration registers Jan 19, 1998 Issued
Array ( [id] => 1526415 [patent_doc_number] => 06353866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Apparatus and method for initializing a universal serial bus device' [patent_app_type] => B1 [patent_app_number] => 09/003925 [patent_app_country] => US [patent_app_date] => 1998-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4613 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353866.pdf [firstpage_image] =>[orig_patent_app_number] => 09003925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003925
Apparatus and method for initializing a universal serial bus device Jan 6, 1998 Issued
Array ( [id] => 4215426 [patent_doc_number] => 06014721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Method and system for transferring data between buses having differing ordering policies' [patent_app_type] => 1 [patent_app_number] => 9/004145 [patent_app_country] => US [patent_app_date] => 1998-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 16665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014721.pdf [firstpage_image] =>[orig_patent_app_number] => 004145 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004145
Method and system for transferring data between buses having differing ordering policies Jan 6, 1998 Issued
Array ( [id] => 4198656 [patent_doc_number] => 06038614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Active volume control with hot key' [patent_app_type] => 1 [patent_app_number] => 9/002594 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038614.pdf [firstpage_image] =>[orig_patent_app_number] => 002594 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002594
Active volume control with hot key Jan 4, 1998 Issued
Array ( [id] => 3996989 [patent_doc_number] => 05961615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method and apparatus for queuing data' [patent_app_type] => 1 [patent_app_number] => 9/002236 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3616 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961615.pdf [firstpage_image] =>[orig_patent_app_number] => 002236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002236
Method and apparatus for queuing data Dec 30, 1997 Issued
Array ( [id] => 4176784 [patent_doc_number] => 06105080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Host adapter DMA controller with automated host reply capability' [patent_app_type] => 1 [patent_app_number] => 9/000681 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5853 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105080.pdf [firstpage_image] =>[orig_patent_app_number] => 000681 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000681
Host adapter DMA controller with automated host reply capability Dec 29, 1997 Issued
Array ( [id] => 4398928 [patent_doc_number] => 06295564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Storage medium having electronic circuit and computer system having the storage medium' [patent_app_type] => 1 [patent_app_number] => 9/000534 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4686 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295564.pdf [firstpage_image] =>[orig_patent_app_number] => 000534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000534
Storage medium having electronic circuit and computer system having the storage medium Dec 29, 1997 Issued
Array ( [id] => 4257327 [patent_doc_number] => 06145040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and system for apportioning computer bus bandwidth' [patent_app_type] => 1 [patent_app_number] => 9/001585 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5027 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145040.pdf [firstpage_image] =>[orig_patent_app_number] => 001585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001585
Method and system for apportioning computer bus bandwidth Dec 29, 1997 Issued
Array ( [id] => 4260647 [patent_doc_number] => 06092207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Computer having a dual mode power supply for implementing a power saving mode' [patent_app_type] => 1 [patent_app_number] => 8/999492 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3430 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092207.pdf [firstpage_image] =>[orig_patent_app_number] => 999492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999492
Computer having a dual mode power supply for implementing a power saving mode Dec 28, 1997 Issued
Array ( [id] => 4171268 [patent_doc_number] => 06125413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Computer system with trigger controlled interface and method' [patent_app_type] => 1 [patent_app_number] => 8/999274 [patent_app_country] => US [patent_app_date] => 1997-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5205 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125413.pdf [firstpage_image] =>[orig_patent_app_number] => 999274 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/999274
Computer system with trigger controlled interface and method Dec 28, 1997 Issued
Array ( [id] => 4203910 [patent_doc_number] => 06151654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method and apparatus for encoded DMA acknowledges' [patent_app_type] => 1 [patent_app_number] => 8/998111 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3803 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151654.pdf [firstpage_image] =>[orig_patent_app_number] => 998111 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998111
Method and apparatus for encoded DMA acknowledges Dec 23, 1997 Issued
Array ( [id] => 4056868 [patent_doc_number] => 05909556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'M&A for exchanging date, status and commands over an hierarchical serial bus assembly using communication packets' [patent_app_type] => 1 [patent_app_number] => 8/980507 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 40 [patent_no_of_words] => 8255 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909556.pdf [firstpage_image] =>[orig_patent_app_number] => 980507 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980507
M&A for exchanging date, status and commands over an hierarchical serial bus assembly using communication packets Nov 30, 1997 Issued
Array ( [id] => 3923912 [patent_doc_number] => 05938754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Fieldbus connector including dual connectors' [patent_app_type] => 1 [patent_app_number] => 8/979968 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4494 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938754.pdf [firstpage_image] =>[orig_patent_app_number] => 979968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979968
Fieldbus connector including dual connectors Nov 25, 1997 Issued
Array ( [id] => 3935814 [patent_doc_number] => 05915105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Integrated circuit I/O using a high performance bus interface' [patent_app_type] => 1 [patent_app_number] => 8/979127 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15059 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915105.pdf [firstpage_image] =>[orig_patent_app_number] => 979127 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979127
Integrated circuit I/O using a high performance bus interface Nov 25, 1997 Issued
Array ( [id] => 4254736 [patent_doc_number] => 06119185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Computer system configuration apparatus and method that performs pre-assignment conflict analysis' [patent_app_type] => 1 [patent_app_number] => 8/980878 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5993 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119185.pdf [firstpage_image] =>[orig_patent_app_number] => 980878 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980878
Computer system configuration apparatus and method that performs pre-assignment conflict analysis Nov 24, 1997 Issued
Array ( [id] => 3985986 [patent_doc_number] => 05919252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Process and apparatus for adaptive bus termination' [patent_app_type] => 1 [patent_app_number] => 8/977640 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1411 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/919/05919252.pdf [firstpage_image] =>[orig_patent_app_number] => 977640 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977640
Process and apparatus for adaptive bus termination Nov 23, 1997 Issued
Array ( [id] => 4239571 [patent_doc_number] => 06088808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Low power consumption semiconductor integrated circuit device and microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/966972 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 11226 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088808.pdf [firstpage_image] =>[orig_patent_app_number] => 966972 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966972
Low power consumption semiconductor integrated circuit device and microprocessor Nov 9, 1997 Issued
Array ( [id] => 4037095 [patent_doc_number] => 05968178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Circuit and method for resetting a microcontroller' [patent_app_type] => 1 [patent_app_number] => 8/963843 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2610 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968178.pdf [firstpage_image] =>[orig_patent_app_number] => 963843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963843
Circuit and method for resetting a microcontroller Nov 3, 1997 Issued
Menu