
Glenn Allen Auve
Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )
| Most Active Art Unit | 2111 |
| Art Unit(s) | 2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305 |
| Total Applications | 2279 |
| Issued Applications | 2041 |
| Pending Applications | 51 |
| Abandoned Applications | 199 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4199779
[patent_doc_number] => 06021458
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Method and apparatus for handling multiple level-triggered and edge-triggered interrupts'
[patent_app_type] => 1
[patent_app_number] => 9/010226
[patent_app_country] => US
[patent_app_date] => 1998-01-21
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[pdf_file] => patents/06/021/06021458.pdf
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Array
(
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[patent_doc_number] => 06052753
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[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Fault tolerant data bus'
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Array
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[patent_doc_number] => 06108733
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[patent_issue_date] => 2000-08-22
[patent_title] => 'Method for extending the available number of configuration registers'
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[patent_app_date] => 1998-01-20
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[patent_drawing_sheets_cnt] => 9
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Array
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[patent_kind] => B1
[patent_issue_date] => 2002-03-05
[patent_title] => 'Apparatus and method for initializing a universal serial bus device'
[patent_app_type] => B1
[patent_app_number] => 09/003925
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Array
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[patent_issue_date] => 2000-01-11
[patent_title] => 'Method and system for transferring data between buses having differing ordering policies'
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Array
(
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[patent_doc_number] => 06038614
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[patent_issue_date] => 2000-03-14
[patent_title] => 'Active volume control with hot key'
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[patent_app_number] => 9/002594
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Array
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[firstpage_image] =>[orig_patent_app_number] => 002236
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/002236 | Method and apparatus for queuing data | Dec 30, 1997 | Issued |
Array
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[id] => 4176784
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[patent_issue_date] => 2000-08-15
[patent_title] => 'Host adapter DMA controller with automated host reply capability'
[patent_app_type] => 1
[patent_app_number] => 9/000681
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[patent_app_date] => 1997-12-30
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[firstpage_image] =>[orig_patent_app_number] => 000681
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/000681 | Host adapter DMA controller with automated host reply capability | Dec 29, 1997 | Issued |
Array
(
[id] => 4398928
[patent_doc_number] => 06295564
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[patent_issue_date] => 2001-09-25
[patent_title] => 'Storage medium having electronic circuit and computer system having the storage medium'
[patent_app_type] => 1
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Array
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[patent_title] => 'Method and system for apportioning computer bus bandwidth'
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Array
(
[id] => 4260647
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[patent_title] => 'Computer having a dual mode power supply for implementing a power saving mode'
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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