Search

Glenn Allen Auve

Examiner (ID: 3740, Phone: (571)272-3623 , Office: P/2185 )

Most Active Art Unit
2111
Art Unit(s)
2181, 2186, 2308, 2111, 2185, 2175, 2781, 2305
Total Applications
2279
Issued Applications
2041
Pending Applications
51
Abandoned Applications
199

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3970332 [patent_doc_number] => 05991841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Memory transactions on a low pin count bus' [patent_app_type] => 1 [patent_app_number] => 8/936848 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9092 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991841.pdf [firstpage_image] =>[orig_patent_app_number] => 936848 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/936848
Memory transactions on a low pin count bus Sep 23, 1997 Issued
Array ( [id] => 3916027 [patent_doc_number] => 05951668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method and system for transferring data between buses having differing ordering policies' [patent_app_type] => 1 [patent_app_number] => 8/934407 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 16662 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951668.pdf [firstpage_image] =>[orig_patent_app_number] => 934407 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934407
Method and system for transferring data between buses having differing ordering policies Sep 18, 1997 Issued
Array ( [id] => 4118137 [patent_doc_number] => 06098144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Solid state data processor with versatile multisource interrupt organization' [patent_app_type] => 1 [patent_app_number] => 8/932980 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6371 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098144.pdf [firstpage_image] =>[orig_patent_app_number] => 932980 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932980
Solid state data processor with versatile multisource interrupt organization Sep 17, 1997 Issued
Array ( [id] => 3970931 [patent_doc_number] => 06000001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Multiple priority accelerated graphics port (AGP) request queue' [patent_app_type] => 1 [patent_app_number] => 8/924755 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 5013 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000001.pdf [firstpage_image] =>[orig_patent_app_number] => 924755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924755
Multiple priority accelerated graphics port (AGP) request queue Sep 4, 1997 Issued
Array ( [id] => 3969004 [patent_doc_number] => 05948089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Fully-pipelined fixed-latency communications system with a real time dynamic bandwidth allocation' [patent_app_type] => 1 [patent_app_number] => 8/924368 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9262 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948089.pdf [firstpage_image] =>[orig_patent_app_number] => 924368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924368
Fully-pipelined fixed-latency communications system with a real time dynamic bandwidth allocation Sep 4, 1997 Issued
Array ( [id] => 3929141 [patent_doc_number] => 06002877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Interrupt control method for controlling an interrupt from a peripheral device to a processor' [patent_app_type] => 1 [patent_app_number] => 8/905857 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3316 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002877.pdf [firstpage_image] =>[orig_patent_app_number] => 905857 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905857
Interrupt control method for controlling an interrupt from a peripheral device to a processor Aug 3, 1997 Issued
Array ( [id] => 3970018 [patent_doc_number] => 05958035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'State machine based bus cycle completion checking in a bus bridge verification system' [patent_app_type] => 1 [patent_app_number] => 8/903704 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9382 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958035.pdf [firstpage_image] =>[orig_patent_app_number] => 903704 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903704
State machine based bus cycle completion checking in a bus bridge verification system Jul 30, 1997 Issued
Array ( [id] => 4037685 [patent_doc_number] => 05926628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Selectable priority bus arbitration scheme' [patent_app_type] => 1 [patent_app_number] => 8/892723 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4147 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926628.pdf [firstpage_image] =>[orig_patent_app_number] => 892723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892723
Selectable priority bus arbitration scheme Jul 14, 1997 Issued
Array ( [id] => 3910069 [patent_doc_number] => 05835739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge' [patent_app_type] => 1 [patent_app_number] => 8/889756 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12537 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835739.pdf [firstpage_image] =>[orig_patent_app_number] => 889756 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889756
Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge Jul 9, 1997 Issued
Array ( [id] => 3878333 [patent_doc_number] => 05793988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Parallel data transfer system and method utilizing different modulating waveforms' [patent_app_type] => 1 [patent_app_number] => 8/887376 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3558 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793988.pdf [firstpage_image] =>[orig_patent_app_number] => 887376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/887376
Parallel data transfer system and method utilizing different modulating waveforms Jul 1, 1997 Issued
Array ( [id] => 4138446 [patent_doc_number] => 06073196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Using communication cycles for connecting and disconnecting devices in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/885110 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 17066 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073196.pdf [firstpage_image] =>[orig_patent_app_number] => 885110 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885110
Using communication cycles for connecting and disconnecting devices in a computer system Jun 29, 1997 Issued
Array ( [id] => 4014580 [patent_doc_number] => 05923860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Apparatus, method and system for remote peripheral component interconnect bus using accelerated graphics port logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/882090 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7683 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923860.pdf [firstpage_image] =>[orig_patent_app_number] => 882090 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882090
Apparatus, method and system for remote peripheral component interconnect bus using accelerated graphics port logic circuits Jun 24, 1997 Issued
Array ( [id] => 4346082 [patent_doc_number] => 06330628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Memory including a data structure used for identifying a communication protocol of a received communication' [patent_app_type] => 1 [patent_app_number] => 8/880683 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330628.pdf [firstpage_image] =>[orig_patent_app_number] => 880683 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880683
Memory including a data structure used for identifying a communication protocol of a received communication Jun 22, 1997 Issued
Array ( [id] => 3973257 [patent_doc_number] => 05978879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Bus bridge apparatus' [patent_app_type] => 1 [patent_app_number] => 8/877208 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13137 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978879.pdf [firstpage_image] =>[orig_patent_app_number] => 877208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877208
Bus bridge apparatus Jun 16, 1997 Issued
Array ( [id] => 3859236 [patent_doc_number] => 05745775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Remotely adjustable price display module' [patent_app_type] => 1 [patent_app_number] => 8/871434 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2372 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745775.pdf [firstpage_image] =>[orig_patent_app_number] => 871434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871434
Remotely adjustable price display module Jun 8, 1997 Issued
Array ( [id] => 3939853 [patent_doc_number] => 05954810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Device for communication between a plurality of functional modules installed in a local unit and an ethernet type external bus' [patent_app_type] => 1 [patent_app_number] => 8/870000 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6311 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954810.pdf [firstpage_image] =>[orig_patent_app_number] => 870000 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870000
Device for communication between a plurality of functional modules installed in a local unit and an ethernet type external bus Jun 4, 1997 Issued
Array ( [id] => 4082011 [patent_doc_number] => 05867720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Printing apparatus and a method therefor, and information processing apparatus and a method therefor' [patent_app_type] => 1 [patent_app_number] => 8/856000 [patent_app_country] => US [patent_app_date] => 1997-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 13844 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867720.pdf [firstpage_image] =>[orig_patent_app_number] => 856000 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/856000
Printing apparatus and a method therefor, and information processing apparatus and a method therefor May 13, 1997 Issued
Array ( [id] => 3787941 [patent_doc_number] => 05774678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method and apparatus for controlling and communicating with business office devices' [patent_app_type] => 1 [patent_app_number] => 8/852413 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2500 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774678.pdf [firstpage_image] =>[orig_patent_app_number] => 852413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852413
Method and apparatus for controlling and communicating with business office devices May 6, 1997 Issued
Array ( [id] => 3829100 [patent_doc_number] => 05771388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'System and method for mapping driver level event function calls from a process-based driver level program to a session-based instrumentation control driver level system' [patent_app_type] => 1 [patent_app_number] => 8/851834 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 36 [patent_no_of_words] => 21425 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771388.pdf [firstpage_image] =>[orig_patent_app_number] => 851834 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851834
System and method for mapping driver level event function calls from a process-based driver level program to a session-based instrumentation control driver level system May 5, 1997 Issued
Array ( [id] => 3849544 [patent_doc_number] => 05761458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Intelligent bus bridge for input/output subsystems in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/850643 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4803 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761458.pdf [firstpage_image] =>[orig_patent_app_number] => 850643 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850643
Intelligent bus bridge for input/output subsystems in a computer system May 1, 1997 Issued
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