Search

Glenn Gossage

Examiner (ID: 17441, Phone: (571)270-7569 , Office: P/2135 )

Most Active Art Unit
2303
Art Unit(s)
2187, 2312, 2185, 2751, 2303, 2759, 2135
Total Applications
1465
Issued Applications
1132
Pending Applications
36
Abandoned Applications
297

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15136667 [patent_doc_number] => 10481799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Data storage device and method including receiving an external multi-access command and generating first and second access commands for first and second nonvolatile memories [patent_app_type] => utility [patent_app_number] => 15/436296 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 11964 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436296 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436296
Data storage device and method including receiving an external multi-access command and generating first and second access commands for first and second nonvolatile memories Feb 16, 2017 Issued
Array ( [id] => 14330699 [patent_doc_number] => 10296368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Hypervisor-independent block-level live browse for access to backed up virtual machine (VM) data and hypervisor-free file-level recovery (block-level pseudo-mount) [patent_app_type] => utility [patent_app_number] => 15/436563 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 39295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436563 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436563
Hypervisor-independent block-level live browse for access to backed up virtual machine (VM) data and hypervisor-free file-level recovery (block-level pseudo-mount) Feb 16, 2017 Issued
Array ( [id] => 14489559 [patent_doc_number] => 10331567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => Prefetch circuit with global quality factor to reduce aggressiveness in low power modes [patent_app_type] => utility [patent_app_number] => 15/435910 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 16555 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435910
Prefetch circuit with global quality factor to reduce aggressiveness in low power modes Feb 16, 2017 Issued
Array ( [id] => 11951240 [patent_doc_number] => 20170255391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'DATA STORAGE APPARATUS, NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN DATA STORAGE APPARATUS CONTROL PROGRAM, AND METHOD FOR CONTROLLING DATA STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/435376 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 15422 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435376 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435376
Data storage apparatus, recording medium and method for selectively duplicating data blocks to another medium based on data block size and dimension information or an axis of obtaining data Feb 16, 2017 Issued
Array ( [id] => 12820627 [patent_doc_number] => 20180165381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => Accelerator for Gather-Update-Scatter Operations [patent_app_type] => utility [patent_app_number] => 15/376172 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376172 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/376172
Accelerator for gather-update-scatter operations including a content-addressable memory (CAM) and CAM controller Dec 11, 2016 Issued
Array ( [id] => 12820096 [patent_doc_number] => 20180165204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => Programmable Memory Prefetcher [patent_app_type] => utility [patent_app_number] => 15/376242 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/376242
Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control register Dec 11, 2016 Issued
Array ( [id] => 11501423 [patent_doc_number] => 20170075608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'SOLID STATE MEMORY UNIT AND METHOD FOR PROTECTING A MEMORY INCLUDING VERIFICATION OF A SEQUENCE OF REQUESTS FOR ACCESS TO PHYSICAL BLOCKS' [patent_app_type] => utility [patent_app_number] => 15/361825 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3980 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/361825
Solid state memory unit and method for protecting a memory including verification of a sequence of requests for access to physical blocks Nov 27, 2016 Issued
Array ( [id] => 12108857 [patent_doc_number] => 09865345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Electronic device including a semiconductor memory having memory arrays with variable resistance storage elements and a bias voltage generator arranged between the arrays' [patent_app_type] => utility [patent_app_number] => 15/362010 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 13760 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/362010
Electronic device including a semiconductor memory having memory arrays with variable resistance storage elements and a bias voltage generator arranged between the arrays Nov 27, 2016 Issued
Array ( [id] => 12591750 [patent_doc_number] => 20180089079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => APPARATUS, MEMORY CONTROLLER, MEMORY MODULE AND METHOD FOR CONTROLLING DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 15/273743 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273743 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273743
Apparatus including a memory controller for controlling direct data transfer between first and second memory modules using direct transfer commands Sep 22, 2016 Issued
Array ( [id] => 15231825 [patent_doc_number] => 10503635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => System and method for adaptive optimization for performance in solid state drives based on segment access frequency [patent_app_type] => utility [patent_app_number] => 15/273573 [patent_app_country] => US [patent_app_date] => 2016-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15273573 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/273573
System and method for adaptive optimization for performance in solid state drives based on segment access frequency Sep 21, 2016 Issued
Array ( [id] => 16278725 [patent_doc_number] => 10761755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Method and apparatus for reclaiming memory blocks in snapshot storage space [patent_app_type] => utility [patent_app_number] => 15/270528 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6443 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270528
Method and apparatus for reclaiming memory blocks in snapshot storage space Sep 19, 2016 Issued
Array ( [id] => 12262396 [patent_doc_number] => 20180081592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'PER-STORAGE CLASS QUALITY OF SERVICE MANAGEMENT WITHIN A DISTRIBUTED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 15/270758 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8190 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270758 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270758
Per-storage class quality of service (QoS) management within a distributed storage network (DSN) where the DSN stores data using dispersed storage error decoding/encoding Sep 19, 2016 Issued
Array ( [id] => 11530825 [patent_doc_number] => 20170090803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'METHOD AND DEVICE FOR CHECKING FALSE SHARING IN DATA BLOCK DELETION' [patent_app_type] => utility [patent_app_number] => 15/270586 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270586
Method and device for checking false sharing in data block deletion using a mapping pointer and weight bits Sep 19, 2016 Issued
Array ( [id] => 11989406 [patent_doc_number] => 20170293561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'REDUCING MEMORY ACCESS BANDWIDTH BASED ON PREDICTION OF MEMORY REQUEST SIZE' [patent_app_type] => utility [patent_app_number] => 15/270331 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7318 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270331 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270331
Reducing memory access bandwidth based on prediction of memory request size Sep 19, 2016 Issued
Array ( [id] => 12262634 [patent_doc_number] => 20180081829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'VIRTUALIZED PROCESS ISOLATION' [patent_app_type] => utility [patent_app_number] => 15/270231 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7351 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270231 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270231
System and method for virtualized process isolation including preventing a kernel from accessing user address space Sep 19, 2016 Issued
Array ( [id] => 12262633 [patent_doc_number] => 20180081830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'HARDWARE SUPERVISION OF PAGE TABLES' [patent_app_type] => utility [patent_app_number] => 15/270708 [patent_app_country] => US [patent_app_date] => 2016-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15270708 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/270708
HARDWARE SUPERVISION OF PAGE TABLES Sep 19, 2016 Abandoned
Array ( [id] => 11951411 [patent_doc_number] => 20170255562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'CACHE DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/269930 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15269930 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/269930
Cache device and semiconductor device including a tag memory storing absence, compression and write state information Sep 18, 2016 Issued
Array ( [id] => 13859889 [patent_doc_number] => 10191663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Using data store accelerator intermediary nodes and write control settings to identify write propagation nodes [patent_app_type] => utility [patent_app_number] => 15/269935 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15269935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/269935
Using data store accelerator intermediary nodes and write control settings to identify write propagation nodes Sep 18, 2016 Issued
Array ( [id] => 14614467 [patent_doc_number] => 10359933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods [patent_app_type] => utility [patent_app_number] => 15/269518 [patent_app_country] => US [patent_app_date] => 2016-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9166 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15269518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/269518
Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods Sep 18, 2016 Issued
Array ( [id] => 13679285 [patent_doc_number] => 20160378379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => MULTI-LAYER MEMORY SYSTEM HAVING MULTIPLE PARTITIONS IN A LAYER [patent_app_type] => utility [patent_app_number] => 15/261419 [patent_app_country] => US [patent_app_date] => 2016-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15261419 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/261419
MULTI-LAYER MEMORY SYSTEM HAVING MULTIPLE PARTITIONS IN A LAYER Sep 8, 2016 Abandoned
Menu