Search

Glenn Gossage

Examiner (ID: 13715, Phone: (571)270-7569 , Office: P/2135 )

Most Active Art Unit
2303
Art Unit(s)
2303, 2187, 2759, 2135, 2312, 2751, 2185
Total Applications
1465
Issued Applications
1132
Pending Applications
36
Abandoned Applications
297

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3760590 [patent_doc_number] => 05717893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Method for managing a cache hierarchy having a least recently used (LRU) global cache and a plurality of LRU destaging local caches containing counterpart datatype partitions' [patent_app_type] => 1 [patent_app_number] => 7/703309 [patent_app_country] => US [patent_app_date] => 1991-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 13985 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717893.pdf [firstpage_image] =>[orig_patent_app_number] => 703309 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/703309
Method for managing a cache hierarchy having a least recently used (LRU) global cache and a plurality of LRU destaging local caches containing counterpart datatype partitions May 19, 1991 Issued
Array ( [id] => 2887760 [patent_doc_number] => 05159571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Semiconductor memory with a circuit for testing characteristics of flip-flops including selectively applied power supply voltages' [patent_app_type] => 1 [patent_app_number] => 7/701333 [patent_app_country] => US [patent_app_date] => 1991-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10947 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 638 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159571.pdf [firstpage_image] =>[orig_patent_app_number] => 701333 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/701333
Semiconductor memory with a circuit for testing characteristics of flip-flops including selectively applied power supply voltages May 8, 1991 Issued
07/696741 A DIGITAL PROCESSING SYSTEM INCLUDING PLURAL MEMORY DEVICES AND DATA TRANSFER OR COPY CIRCUITRY May 6, 1991 Abandoned
Array ( [id] => 2836465 [patent_doc_number] => 05117394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-26 [patent_title] => 'High speed differential sense amplifier for use with single transistor memory cells' [patent_app_type] => 1 [patent_app_number] => 7/698257 [patent_app_country] => US [patent_app_date] => 1991-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3117 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/117/05117394.pdf [firstpage_image] =>[orig_patent_app_number] => 698257 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/698257
High speed differential sense amplifier for use with single transistor memory cells May 5, 1991 Issued
Array ( [id] => 3111250 [patent_doc_number] => 05319768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Control circuit for resetting a snoop valid bit in a dual port cache tag memory' [patent_app_type] => 1 [patent_app_number] => 7/694451 [patent_app_country] => US [patent_app_date] => 1991-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2834 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/319/05319768.pdf [firstpage_image] =>[orig_patent_app_number] => 694451 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/694451
Control circuit for resetting a snoop valid bit in a dual port cache tag memory Apr 30, 1991 Issued
Array ( [id] => 3007965 [patent_doc_number] => 05367682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Data processing virus protection circuitry including a permanent memory for storing a redundant partition table' [patent_app_type] => 1 [patent_app_number] => 7/692619 [patent_app_country] => US [patent_app_date] => 1991-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1957 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367682.pdf [firstpage_image] =>[orig_patent_app_number] => 692619 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/692619
Data processing virus protection circuitry including a permanent memory for storing a redundant partition table Apr 28, 1991 Issued
Array ( [id] => 2795115 [patent_doc_number] => 05142494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Memory based line-delay architecture' [patent_app_type] => 1 [patent_app_number] => 7/692797 [patent_app_country] => US [patent_app_date] => 1991-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4581 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142494.pdf [firstpage_image] =>[orig_patent_app_number] => 692797 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/692797
Memory based line-delay architecture Apr 28, 1991 Issued
Array ( [id] => 3111163 [patent_doc_number] => 05319764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Address detection circuit using a memory' [patent_app_type] => 1 [patent_app_number] => 7/690336 [patent_app_country] => US [patent_app_date] => 1991-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 2782 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/319/05319764.pdf [firstpage_image] =>[orig_patent_app_number] => 690336 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/690336
Address detection circuit using a memory Apr 25, 1991 Issued
07/691568 FLASH EEPROM MEMORY SYSTEMS AND METHODS OF USING THEM Apr 24, 1991 Abandoned
07/691240 LRU POINTER UPDATING IN A CONTROLLER FOR TWO-WAY SET ASSOCIATIVE CACHE Apr 24, 1991 Abandoned
Array ( [id] => 3009203 [patent_doc_number] => 05359562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Semiconductor memory having polycrystalline silicon load resistors and CMOS peripheral circuitry' [patent_app_type] => 1 [patent_app_number] => 7/684867 [patent_app_country] => US [patent_app_date] => 1991-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 43 [patent_no_of_words] => 7653 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359562.pdf [firstpage_image] =>[orig_patent_app_number] => 684867 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/684867
Semiconductor memory having polycrystalline silicon load resistors and CMOS peripheral circuitry Apr 14, 1991 Issued
Array ( [id] => 3024231 [patent_doc_number] => 05276843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Dynamic RAM array for emulating a static RAM array' [patent_app_type] => 1 [patent_app_number] => 7/684428 [patent_app_country] => US [patent_app_date] => 1991-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3435 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276843.pdf [firstpage_image] =>[orig_patent_app_number] => 684428 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/684428
Dynamic RAM array for emulating a static RAM array Apr 11, 1991 Issued
Array ( [id] => 3100975 [patent_doc_number] => 05298815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'Cascode amplifier circuitry for amplifying differential signals' [patent_app_type] => 1 [patent_app_number] => 7/683259 [patent_app_country] => US [patent_app_date] => 1991-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7574 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/298/05298815.pdf [firstpage_image] =>[orig_patent_app_number] => 683259 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/683259
Cascode amplifier circuitry for amplifying differential signals Apr 9, 1991 Issued
07/683116 MEMORY DEVICE WITH END-OF-CYCLE PRECHARGE Apr 7, 1991 Abandoned
Array ( [id] => 2763031 [patent_doc_number] => 05072423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-10 [patent_title] => 'Optical information memory medium recording and erasing information including gallium and antimony' [patent_app_type] => 1 [patent_app_number] => 7/681457 [patent_app_country] => US [patent_app_date] => 1991-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 36 [patent_no_of_words] => 11770 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/072/05072423.pdf [firstpage_image] =>[orig_patent_app_number] => 681457 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/681457
Optical information memory medium recording and erasing information including gallium and antimony Apr 3, 1991 Issued
Array ( [id] => 3602717 [patent_doc_number] => 05488709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Cache including decoupling register circuits' [patent_app_type] => 1 [patent_app_number] => 7/678912 [patent_app_country] => US [patent_app_date] => 1991-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 70 [patent_no_of_words] => 33868 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488709.pdf [firstpage_image] =>[orig_patent_app_number] => 678912 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/678912
Cache including decoupling register circuits Mar 31, 1991 Issued
Array ( [id] => 2830771 [patent_doc_number] => 05173878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-22 [patent_title] => 'Semiconductor memory including address multiplexing circuitry for changing the order of supplying row and column addresses between read and write cycles' [patent_app_type] => 1 [patent_app_number] => 7/671137 [patent_app_country] => US [patent_app_date] => 1991-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 59 [patent_no_of_words] => 4361 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/173/05173878.pdf [firstpage_image] =>[orig_patent_app_number] => 671137 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/671137
Semiconductor memory including address multiplexing circuitry for changing the order of supplying row and column addresses between read and write cycles Mar 17, 1991 Issued
07/665021 METHOD OF OPERATING A CACHE MEMORY INCLUDING DETERMINING DESIRABILITY OF CACHE-AHEAD OR CACHE-BEHIND BASED ON A NUMBER OF AVAILIABLE I/O OPERATIONS Mar 4, 1991 Abandoned
Array ( [id] => 2904658 [patent_doc_number] => 05270981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Field memory device functioning as a variable stage shift register with gated feedback from its output to its input' [patent_app_type] => 1 [patent_app_number] => 7/664477 [patent_app_country] => US [patent_app_date] => 1991-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4282 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270981.pdf [firstpage_image] =>[orig_patent_app_number] => 664477 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/664477
Field memory device functioning as a variable stage shift register with gated feedback from its output to its input Mar 3, 1991 Issued
Array ( [id] => 2870355 [patent_doc_number] => 05166901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Programmable memory cell structure including a refractory metal barrier layer' [patent_app_type] => 1 [patent_app_number] => 7/662381 [patent_app_country] => US [patent_app_date] => 1991-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4672 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166901.pdf [firstpage_image] =>[orig_patent_app_number] => 662381 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/662381
Programmable memory cell structure including a refractory metal barrier layer Feb 25, 1991 Issued
Menu