| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 11292730
[patent_doc_number] => 20160342662
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-11-24
[patent_title] => 'MULTI-STAGE TCAM SEARCH'
[patent_app_type] => utility
[patent_app_number] => 15/224689
[patent_app_country] => US
[patent_app_date] => 2016-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5105
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224689
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/224689 | MULTI-STAGE TCAM SEARCH | Jul 31, 2016 | Abandoned |
Array
(
[id] => 11116944
[patent_doc_number] => 20160313918
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-27
[patent_title] => 'STORAGE DEVICE ACCESS USING UNPRIVILEGED SOFTWARE CODE'
[patent_app_type] => utility
[patent_app_number] => 15/203527
[patent_app_country] => US
[patent_app_date] => 2016-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9027
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15203527
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/203527 | Storage device access using unprivileged software code | Jul 5, 2016 | Issued |
Array
(
[id] => 14149181
[patent_doc_number] => 10254970
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-04-09
[patent_title] => System, method and computer readable medium for obtaining consistent read performance for a plurality of flash drives or raid groups using workload and capacity limits
[patent_app_type] => utility
[patent_app_number] => 15/198772
[patent_app_country] => US
[patent_app_date] => 2016-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 52
[patent_no_of_words] => 64479
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198772
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/198772 | System, method and computer readable medium for obtaining consistent read performance for a plurality of flash drives or raid groups using workload and capacity limits | Jun 29, 2016 | Issued |
Array
(
[id] => 11614434
[patent_doc_number] => 09652291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-16
[patent_title] => 'System and method utilizing a shared cache to provide zero copy memory mapped database'
[patent_app_type] => utility
[patent_app_number] => 15/173526
[patent_app_country] => US
[patent_app_date] => 2016-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5289
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15173526
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/173526 | System and method utilizing a shared cache to provide zero copy memory mapped database | Jun 2, 2016 | Issued |
Array
(
[id] => 16370974
[patent_doc_number] => 10802729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-13
[patent_title] => Apparatus and method for sharing pages including enforcing ownership rights independently of privilege level
[patent_app_type] => utility
[patent_app_number] => 15/574549
[patent_app_country] => US
[patent_app_date] => 2016-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 15785
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574549
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/574549 | Apparatus and method for sharing pages including enforcing ownership rights independently of privilege level | Apr 25, 2016 | Issued |
Array
(
[id] => 12713770
[patent_doc_number] => 20180129756
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-10
[patent_title] => SEMICONDUCTOR DEVICE AND INFORMATION WRITING/READING METHOD
[patent_app_type] => utility
[patent_app_number] => 15/574690
[patent_app_country] => US
[patent_app_date] => 2016-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19329
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574690
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/574690 | Writing method and semiconductor device including a search memory mat with write processing terminated when one piece of divided key data is successfully written | Apr 17, 2016 | Issued |
Array
(
[id] => 11981834
[patent_doc_number] => 20170285988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'MEMORY POWER COORDINATION'
[patent_app_type] => utility
[patent_app_number] => 15/090301
[patent_app_country] => US
[patent_app_date] => 2016-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 10924
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090301
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/090301 | Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions | Apr 3, 2016 | Issued |
Array
(
[id] => 11606355
[patent_doc_number] => 20170123658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-04
[patent_title] => 'METHOD AND APPARATUS FOR PARALLEL PROCESSING DATA'
[patent_app_type] => utility
[patent_app_number] => 15/090111
[patent_app_country] => US
[patent_app_date] => 2016-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4490
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090111
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/090111 | Method and apparatus for parallel processing data including bypassing memory address alias checking | Apr 3, 2016 | Issued |
Array
(
[id] => 14555689
[patent_doc_number] => 10346306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-09
[patent_title] => Processor and method for memory performance monitoring utilizing a monitor flag and first and second allocators for allocating virtual memory regions
[patent_app_type] => utility
[patent_app_number] => 15/089534
[patent_app_country] => US
[patent_app_date] => 2016-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 13320
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089534
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089534 | Processor and method for memory performance monitoring utilizing a monitor flag and first and second allocators for allocating virtual memory regions | Apr 1, 2016 | Issued |
Array
(
[id] => 14175351
[patent_doc_number] => 10261688
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-16
[patent_title] => Performing search and replace operations in a memory device using command parameters and a storage controller without transferring data to a processor
[patent_app_type] => utility
[patent_app_number] => 15/089503
[patent_app_country] => US
[patent_app_date] => 2016-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 11177
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 331
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089503
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089503 | Performing search and replace operations in a memory device using command parameters and a storage controller without transferring data to a processor | Apr 1, 2016 | Issued |
Array
(
[id] => 11982147
[patent_doc_number] => 20170286301
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'METHOD, SYSTEM, AND APPARATUS FOR A COHERENCY TASK LIST TO MINIMIZE CACHE SNOOPING BETWEEN CPU AND FPGA'
[patent_app_type] => utility
[patent_app_number] => 15/089467
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9032
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089467
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089467 | METHOD, SYSTEM, AND APPARATUS FOR A COHERENCY TASK LIST TO MINIMIZE CACHE SNOOPING BETWEEN CPU AND FPGA | Mar 31, 2016 | Abandoned |
Array
(
[id] => 14523621
[patent_doc_number] => 10339072
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-02
[patent_title] => Read delivery for memory subsystem with narrow bandwidth repeater channel
[patent_app_type] => utility
[patent_app_number] => 15/089455
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 29006
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089455
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089455 | Read delivery for memory subsystem with narrow bandwidth repeater channel | Mar 31, 2016 | Issued |
Array
(
[id] => 15472885
[patent_doc_number] => 10552320
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-02-04
[patent_title] => Using a projected out of memory score to selectively terminate a process without transitioning to a background mode
[patent_app_type] => utility
[patent_app_number] => 15/089439
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 10033
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089439
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089439 | Using a projected out of memory score to selectively terminate a process without transitioning to a background mode | Mar 31, 2016 | Issued |
Array
(
[id] => 11981839
[patent_doc_number] => 20170285992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL'
[patent_app_type] => utility
[patent_app_number] => 15/089453
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 18185
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089453
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089453 | MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL | Mar 31, 2016 | Abandoned |
Array
(
[id] => 15248111
[patent_doc_number] => 10509580
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-17
[patent_title] => Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match
[patent_app_type] => utility
[patent_app_number] => 15/089456
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 14590
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089456
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089456 | Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match | Mar 31, 2016 | Issued |
Array
(
[id] => 11982540
[patent_doc_number] => 20170286694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'METHOD AND APPARATUS FOR PERFORMING PROTECTED WALK BASED SHADOW PAGING'
[patent_app_type] => utility
[patent_app_number] => 15/089376
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9580
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089376
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089376 | Method and apparatus for performing protected walk-based shadow paging using multiple stages of page tables | Mar 31, 2016 | Issued |
Array
(
[id] => 11985695
[patent_doc_number] => 20170289850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'WRITE DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL'
[patent_app_type] => utility
[patent_app_number] => 15/089454
[patent_app_country] => US
[patent_app_date] => 2016-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 29311
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15089454
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/089454 | WRITE DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL | Mar 31, 2016 | Abandoned |
Array
(
[id] => 11482357
[patent_doc_number] => 09588904
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-03-07
[patent_title] => 'Host apparatus to independently schedule maintenance operations for respective virtual block devices in the flash memory dependent on information received from a memory controller'
[patent_app_type] => utility
[patent_app_number] => 15/053372
[patent_app_country] => US
[patent_app_date] => 2016-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 15178
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15053372
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/053372 | Host apparatus to independently schedule maintenance operations for respective virtual block devices in the flash memory dependent on information received from a memory controller | Feb 24, 2016 | Issued |
Array
(
[id] => 11810774
[patent_doc_number] => 09715343
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-25
[patent_title] => 'Multidimensional partitioned storage array and method utilizing input shifters to allow multiple entire columns or rows to be accessed in a single clock cycle'
[patent_app_type] => utility
[patent_app_number] => 15/051059
[patent_app_country] => US
[patent_app_date] => 2016-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 47
[patent_no_of_words] => 24397
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 368
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051059
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/051059 | Multidimensional partitioned storage array and method utilizing input shifters to allow multiple entire columns or rows to be accessed in a single clock cycle | Feb 22, 2016 | Issued |
Array
(
[id] => 11072517
[patent_doc_number] => 20160269481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-15
[patent_title] => 'Multi-Cluster Container Replication'
[patent_app_type] => utility
[patent_app_number] => 14/979035
[patent_app_country] => US
[patent_app_date] => 2015-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 16286
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979035
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/979035 | Multi-Cluster Container Replication | Dec 21, 2015 | Abandoned |