| Application number | Title of the application | Filing Date | Status |
|---|
| 07/438713 | FLOATING GATE SEMICONDUCTOR NONVOLATILE MEMORY HAVING IMPURITY DOPED REGIONS FOR LOW VOLTAGE OPERATION | Nov 16, 1989 | Abandoned |
Array
(
[id] => 2992563
[patent_doc_number] => 05253352
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-12
[patent_title] => 'Method and apparatus for pipelining cache accesses using anticipatory initiation of cache read'
[patent_app_type] => 1
[patent_app_number] => 7/435880
[patent_app_country] => US
[patent_app_date] => 1989-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6424
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/253/05253352.pdf
[firstpage_image] =>[orig_patent_app_number] => 435880
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/435880 | Method and apparatus for pipelining cache accesses using anticipatory initiation of cache read | Nov 12, 1989 | Issued |
| 07/435152 | METHOD AND APPARATUS FOR READING WRITE-ONLY OUTPUT PORTS | Nov 12, 1989 | Abandoned |
| 07/433013 | DYNAMIC SEMICONDUCTOR MEMORY DEVICE HAVING AN IMPROVED SENSE AMPLIFIER LAYOUT ARRANGEMENT | Nov 6, 1989 | Abandoned |
| 07/430983 | SYSTEM FOR RECORDING/REPRODUCING CHARGE LATENT IMAGE | Nov 2, 1989 | Abandoned |
Array
(
[id] => 2743980
[patent_doc_number] => 05051959
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-24
[patent_title] => 'Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type'
[patent_app_type] => 1
[patent_app_number] => 7/430968
[patent_app_country] => US
[patent_app_date] => 1989-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6826
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 267
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/051/05051959.pdf
[firstpage_image] =>[orig_patent_app_number] => 430968
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/430968 | Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type | Oct 31, 1989 | Issued |
| 07/430915 | BIT LINE STRUCTURE FOR SEMICONDUCTOR MEMORY DEVICE | Oct 30, 1989 | Abandoned |
| 07/424712 | MEMORY SYSTEM EMPLOYING EXTENDED MEMORY CAPACITY DETECTION CIRCUIT | Oct 19, 1989 | Abandoned |
Array
(
[id] => 2698383
[patent_doc_number] => 05050127
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-17
[patent_title] => 'Memory device with improved common data line bias arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/423947
[patent_app_country] => US
[patent_app_date] => 1989-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 8015
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 353
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/050/05050127.pdf
[firstpage_image] =>[orig_patent_app_number] => 423947
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/423947 | Memory device with improved common data line bias arrangement | Oct 18, 1989 | Issued |
Array
(
[id] => 3089933
[patent_doc_number] => 05297267
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'System and method for serialization control of accesses to a common main storage'
[patent_app_type] => 1
[patent_app_number] => 7/420780
[patent_app_country] => US
[patent_app_date] => 1989-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7792
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/297/05297267.pdf
[firstpage_image] =>[orig_patent_app_number] => 420780
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/420780 | System and method for serialization control of accesses to a common main storage | Oct 11, 1989 | Issued |
Array
(
[id] => 2668090
[patent_doc_number] => 04979149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-18
[patent_title] => 'Non-volatile memory device including a micro-mechanical storage element'
[patent_app_type] => 1
[patent_app_number] => 7/417338
[patent_app_country] => US
[patent_app_date] => 1989-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 5733
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/979/04979149.pdf
[firstpage_image] =>[orig_patent_app_number] => 417338
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/417338 | Non-volatile memory device including a micro-mechanical storage element | Oct 4, 1989 | Issued |
Array
(
[id] => 3110421
[patent_doc_number] => 05293599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Process for partially swapping real storage areas used by a program between a real storage and an auxiliary storage'
[patent_app_type] => 1
[patent_app_number] => 7/416992
[patent_app_country] => US
[patent_app_date] => 1989-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5494
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/293/05293599.pdf
[firstpage_image] =>[orig_patent_app_number] => 416992
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/416992 | Process for partially swapping real storage areas used by a program between a real storage and an auxiliary storage | Oct 3, 1989 | Issued |
Array
(
[id] => 2861803
[patent_doc_number] => 05089993
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-02-18
[patent_title] => 'Memory module arranged for data and parity bits'
[patent_app_type] => 1
[patent_app_number] => 7/415074
[patent_app_country] => US
[patent_app_date] => 1989-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 4957
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/089/05089993.pdf
[firstpage_image] =>[orig_patent_app_number] => 415074
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/415074 | Memory module arranged for data and parity bits | Sep 28, 1989 | Issued |
| 07/411266 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE | Sep 24, 1989 | Abandoned |
Array
(
[id] => 2753340
[patent_doc_number] => 05029128
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-02
[patent_title] => 'Semiconductor memory device with ferroelectric capacitor cells with a plate to which a mid-level voltage is applied'
[patent_app_type] => 1
[patent_app_number] => 7/412123
[patent_app_country] => US
[patent_app_date] => 1989-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 6876
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/029/05029128.pdf
[firstpage_image] =>[orig_patent_app_number] => 412123
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/412123 | Semiconductor memory device with ferroelectric capacitor cells with a plate to which a mid-level voltage is applied | Sep 24, 1989 | Issued |
Array
(
[id] => 2605369
[patent_doc_number] => 04975878
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-04
[patent_title] => 'Programmable memory data protection scheme'
[patent_app_type] => 1
[patent_app_number] => 7/409958
[patent_app_country] => US
[patent_app_date] => 1989-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5252
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 274
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/975/04975878.pdf
[firstpage_image] =>[orig_patent_app_number] => 409958
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/409958 | Programmable memory data protection scheme | Sep 17, 1989 | Issued |
| 07/408013 | SEMICONDCUTOR MEMORY DEVICE HAVING FLASH WRITE FUNCTION | Sep 14, 1989 | Abandoned |
| 07/406798 | HIGH CAPACITY DATA STORAGE METHOD AND SYSTEM USING PLURAL HEADS AND CIRCUITRY FOR MONITORING FREQUENTLY ACCESSED DATA RECORDS | Sep 12, 1989 | Abandoned |
Array
(
[id] => 2857829
[patent_doc_number] => 05107465
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-21
[patent_title] => 'Asynchronous/synchronous pipeline dual mode memory access circuit and method'
[patent_app_type] => 1
[patent_app_number] => 7/407403
[patent_app_country] => US
[patent_app_date] => 1989-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2304
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/107/05107465.pdf
[firstpage_image] =>[orig_patent_app_number] => 407403
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/407403 | Asynchronous/synchronous pipeline dual mode memory access circuit and method | Sep 12, 1989 | Issued |
| 07/405800 | APPARATUS AND METHOD FOR MAINTAINING CACHE/MAIN MEMORY CONSISTENCY FOR WRITE OPERATIONS OF LESS THAN A WORD IN WIDTH | Sep 10, 1989 | Abandoned |
