Search

Gopal C. Ray

Examiner (ID: 16225)

Most Active Art Unit
2781
Art Unit(s)
2307, 2781, 2305, 2111, 2181, 2787, 2308
Total Applications
1625
Issued Applications
1400
Pending Applications
56
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1046295 [patent_doc_number] => 06868466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Apparatus and method for packet ingress interrupt moderation' [patent_app_type] => utility [patent_app_number] => 09/967300 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6962 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868466.pdf [firstpage_image] =>[orig_patent_app_number] => 09967300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/967300
Apparatus and method for packet ingress interrupt moderation Sep 26, 2001 Issued
Array ( [id] => 1092789 [patent_doc_number] => 06829667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method and system for improved processing of CPU intensive communications protocols by disabling per frame interrupts for an interrupt period' [patent_app_type] => B2 [patent_app_number] => 09/951538 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4600 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829667.pdf [firstpage_image] =>[orig_patent_app_number] => 09951538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951538
Method and system for improved processing of CPU intensive communications protocols by disabling per frame interrupts for an interrupt period Sep 13, 2001 Issued
Array ( [id] => 1165507 [patent_doc_number] => 06772259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Interrupt handlers used in different modes of operations' [patent_app_type] => B2 [patent_app_number] => 09/952852 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5754 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772259.pdf [firstpage_image] =>[orig_patent_app_number] => 09952852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952852
Interrupt handlers used in different modes of operations Sep 11, 2001 Issued
Array ( [id] => 1177442 [patent_doc_number] => 06760804 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Apparatus and method for providing an interface between legacy applications and a wireless communication network' [patent_app_type] => B1 [patent_app_number] => 09/954113 [patent_app_country] => US [patent_app_date] => 2001-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7214 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760804.pdf [firstpage_image] =>[orig_patent_app_number] => 09954113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/954113
Apparatus and method for providing an interface between legacy applications and a wireless communication network Sep 10, 2001 Issued
Array ( [id] => 6294239 [patent_doc_number] => 20020056018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Method and apparatus implementing a tuned stub SCSI topology' [patent_app_type] => new [patent_app_number] => 09/948872 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11599 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056018.pdf [firstpage_image] =>[orig_patent_app_number] => 09948872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948872
Method and apparatus implementing a tuned stub SCSI topology Sep 6, 2001 Issued
Array ( [id] => 1169411 [patent_doc_number] => 06763418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Request bus arbitration' [patent_app_type] => B1 [patent_app_number] => 09/948925 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7644 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763418.pdf [firstpage_image] =>[orig_patent_app_number] => 09948925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948925
Request bus arbitration Sep 6, 2001 Issued
Array ( [id] => 6751945 [patent_doc_number] => 20030046466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Bus extension apparatus and methods' [patent_app_type] => new [patent_app_number] => 09/947812 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046466.pdf [firstpage_image] =>[orig_patent_app_number] => 09947812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947812
Bus extender and formatter apparatus and methods Sep 4, 2001 Issued
Array ( [id] => 6751944 [patent_doc_number] => 20030046465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'System and method for servicing interrupts' [patent_app_type] => new [patent_app_number] => 09/947303 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4245 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046465.pdf [firstpage_image] =>[orig_patent_app_number] => 09947303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947303
System and method for servicing interrupts Sep 4, 2001 Issued
Array ( [id] => 765072 [patent_doc_number] => 07016992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Electronic mail system' [patent_app_type] => utility [patent_app_number] => 09/929279 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 8344 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/016/07016992.pdf [firstpage_image] =>[orig_patent_app_number] => 09929279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929279
Electronic mail system Aug 14, 2001 Issued
Array ( [id] => 6839855 [patent_doc_number] => 20030037195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'On-board input/output port' [patent_app_type] => new [patent_app_number] => 09/929755 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1715 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037195.pdf [firstpage_image] =>[orig_patent_app_number] => 09929755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929755
On-board input/output port Aug 13, 2001 Abandoned
Array ( [id] => 6533541 [patent_doc_number] => 20020026604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Fault resilient/fault tolerant computing' [patent_app_type] => new [patent_app_number] => 09/925487 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11428 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026604.pdf [firstpage_image] =>[orig_patent_app_number] => 09925487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925487
Fault resilient/fault tolerant computing Aug 9, 2001 Issued
Array ( [id] => 1082968 [patent_doc_number] => 06836815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Layered crossbar for interconnection of multiple processors and shared memories' [patent_app_type] => B1 [patent_app_number] => 09/925137 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13049 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836815.pdf [firstpage_image] =>[orig_patent_app_number] => 09925137 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/925137
Layered crossbar for interconnection of multiple processors and shared memories Aug 7, 2001 Issued
Array ( [id] => 6717346 [patent_doc_number] => 20030028694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Prefetching data for peripheral component interconnect devices' [patent_app_type] => new [patent_app_number] => 09/922235 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5734 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028694.pdf [firstpage_image] =>[orig_patent_app_number] => 09922235 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922235
Prefetching data for peripheral component interconnect devices Aug 1, 2001 Issued
Array ( [id] => 6717344 [patent_doc_number] => 20030028692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Method and apparatus for transmitting data' [patent_app_type] => new [patent_app_number] => 09/923248 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3764 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028692.pdf [firstpage_image] =>[orig_patent_app_number] => 09923248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923248
Method and apparatus for transmitting data that utilizes delay elements to reduce capacitive coupling Aug 1, 2001 Issued
Array ( [id] => 1178881 [patent_doc_number] => 06757771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Stack switching mechanism in a computer system' [patent_app_type] => B2 [patent_app_number] => 09/920459 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8683 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757771.pdf [firstpage_image] =>[orig_patent_app_number] => 09920459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920459
Stack switching mechanism in a computer system Jul 31, 2001 Issued
Array ( [id] => 1196872 [patent_doc_number] => 06732207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Fast serial interface used for controller to robot communications' [patent_app_type] => B2 [patent_app_number] => 09/918973 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3559 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732207.pdf [firstpage_image] =>[orig_patent_app_number] => 09918973 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918973
Fast serial interface used for controller to robot communications Jul 30, 2001 Issued
Array ( [id] => 1109712 [patent_doc_number] => 06813676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Host interface bypass on a fabric based array controller' [patent_app_type] => B1 [patent_app_number] => 09/916773 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2510 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813676.pdf [firstpage_image] =>[orig_patent_app_number] => 09916773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916773
Host interface bypass on a fabric based array controller Jul 26, 2001 Issued
Array ( [id] => 5990610 [patent_doc_number] => 20020099888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures' [patent_app_type] => new [patent_app_number] => 09/915213 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8733 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099888.pdf [firstpage_image] =>[orig_patent_app_number] => 09915213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915213
I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures Jul 24, 2001 Issued
Array ( [id] => 6636935 [patent_doc_number] => 20020016879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Resource locking and thread synchronization in a multiprocessor environment' [patent_app_type] => new [patent_app_number] => 09/912870 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3982 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20020016879.pdf [firstpage_image] =>[orig_patent_app_number] => 09912870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/912870
Resource locking and thread synchronization in a multiprocessor environment Jul 24, 2001 Issued
Array ( [id] => 1154956 [patent_doc_number] => 06779068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Portable computer and automatic setting method of master/slave devices for the same' [patent_app_type] => B2 [patent_app_number] => 09/910917 [patent_app_country] => US [patent_app_date] => 2001-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779068.pdf [firstpage_image] =>[orig_patent_app_number] => 09910917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/910917
Portable computer and automatic setting method of master/slave devices for the same Jul 23, 2001 Issued
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