Search

Gopal C. Ray

Examiner (ID: 16225)

Most Active Art Unit
2781
Art Unit(s)
2307, 2781, 2305, 2111, 2181, 2787, 2308
Total Applications
1625
Issued Applications
1400
Pending Applications
56
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1539942 [patent_doc_number] => 06338098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-08 [patent_title] => 'Processor with internal register for peripheral status' [patent_app_type] => B2 [patent_app_number] => 09/771499 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4575 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338098.pdf [firstpage_image] =>[orig_patent_app_number] => 09771499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771499
Processor with internal register for peripheral status Jan 25, 2001 Issued
Array ( [id] => 7118675 [patent_doc_number] => 20010001868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Computer system including core logic unit with internal register for peripheral status' [patent_app_type] => new-utility [patent_app_number] => 09/764631 [patent_app_country] => US [patent_app_date] => 2001-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4473 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001868.pdf [firstpage_image] =>[orig_patent_app_number] => 09764631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/764631
Computer system including core logic unit with internal register for peripheral status Jan 16, 2001 Issued
Array ( [id] => 6085456 [patent_doc_number] => 20020083249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Methods and systems for intelligent I/O controller with channel expandability via master/slave configuration' [patent_app_type] => new [patent_app_number] => 09/748324 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083249.pdf [firstpage_image] =>[orig_patent_app_number] => 09748324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748324
Methods and systems for intelligent I/O controller with channel expandability via master/slave configuration Dec 25, 2000 Issued
Array ( [id] => 1186324 [patent_doc_number] => 06742073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Bus controller technique to control N buses' [patent_app_type] => B1 [patent_app_number] => 09/746162 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2206 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742073.pdf [firstpage_image] =>[orig_patent_app_number] => 09746162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746162
Bus controller technique to control N buses Dec 25, 2000 Issued
Array ( [id] => 1240835 [patent_doc_number] => 06691202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Ethernet cross point switch with reduced connections by using column control buses' [patent_app_type] => B2 [patent_app_number] => 09/748565 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9316 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691202.pdf [firstpage_image] =>[orig_patent_app_number] => 09748565 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748565
Ethernet cross point switch with reduced connections by using column control buses Dec 21, 2000 Issued
Array ( [id] => 7631582 [patent_doc_number] => 06665755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'External memory engine selectable pipeline architecture' [patent_app_type] => B2 [patent_app_number] => 09/742286 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 18909 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665755.pdf [firstpage_image] =>[orig_patent_app_number] => 09742286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742286
External memory engine selectable pipeline architecture Dec 21, 2000 Issued
Array ( [id] => 7633102 [patent_doc_number] => 06658518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Serial bus connection controller for establishing a logical connection between initiator and target nodes in a first-to-win racing condition' [patent_app_type] => B2 [patent_app_number] => 09/745961 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 6342 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658518.pdf [firstpage_image] =>[orig_patent_app_number] => 09745961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745961
Serial bus connection controller for establishing a logical connection between initiator and target nodes in a first-to-win racing condition Dec 21, 2000 Issued
Array ( [id] => 1296981 [patent_doc_number] => 06633937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'GPIB system and method which performs autopolling using heuristics' [patent_app_type] => B2 [patent_app_number] => 09/746734 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5296 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633937.pdf [firstpage_image] =>[orig_patent_app_number] => 09746734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746734
GPIB system and method which performs autopolling using heuristics Dec 20, 2000 Issued
Array ( [id] => 7630013 [patent_doc_number] => 06636926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Shared memory multiprocessor performing cache coherence control and node controller therefor' [patent_app_type] => B2 [patent_app_number] => 09/740816 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 13367 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636926.pdf [firstpage_image] =>[orig_patent_app_number] => 09740816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740816
Shared memory multiprocessor performing cache coherence control and node controller therefor Dec 20, 2000 Issued
Array ( [id] => 1192430 [patent_doc_number] => 06735660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Sideband signal transmission between host and input/output adapter' [patent_app_type] => B1 [patent_app_number] => 09/747081 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6031 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735660.pdf [firstpage_image] =>[orig_patent_app_number] => 09747081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/747081
Sideband signal transmission between host and input/output adapter Dec 20, 2000 Issued
Array ( [id] => 1200904 [patent_doc_number] => 06728815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method and structure for supporting data streaming by a SCSI target during the data in phase of the packetized SCSI protocol' [patent_app_type] => B1 [patent_app_number] => 09/745105 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728815.pdf [firstpage_image] =>[orig_patent_app_number] => 09745105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745105
Method and structure for supporting data streaming by a SCSI target during the data in phase of the packetized SCSI protocol Dec 19, 2000 Issued
Array ( [id] => 1225515 [patent_doc_number] => 06704830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Apparatus for wire-or bus expansion between two instrument chassis' [patent_app_type] => B1 [patent_app_number] => 09/741569 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3947 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704830.pdf [firstpage_image] =>[orig_patent_app_number] => 09741569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741569
Apparatus for wire-or bus expansion between two instrument chassis Dec 18, 2000 Issued
Array ( [id] => 1165469 [patent_doc_number] => 06772255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method and apparatus for filtering lock requests' [patent_app_type] => B2 [patent_app_number] => 09/738895 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17237 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772255.pdf [firstpage_image] =>[orig_patent_app_number] => 09738895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738895
Method and apparatus for filtering lock requests Dec 13, 2000 Issued
Array ( [id] => 6757421 [patent_doc_number] => 20030005198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'System carrier for freely programmable blocks' [patent_app_type] => new [patent_app_number] => 10/204024 [patent_app_country] => US [patent_app_date] => 2002-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2115 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005198.pdf [firstpage_image] =>[orig_patent_app_number] => 10204024 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/204024
System carrier for freely programmable blocks Dec 13, 2000 Issued
Array ( [id] => 7118687 [patent_doc_number] => 20010001880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Real-time power conservation and thermal management for electronic devices' [patent_app_type] => new-utility [patent_app_number] => 09/727597 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11362 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001880.pdf [firstpage_image] =>[orig_patent_app_number] => 09727597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/727597
Real-time power conservation and thermal management for electronic devices Nov 30, 2000 Issued
Array ( [id] => 1314193 [patent_doc_number] => 06622189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method and system for low overhead spin lock instrumentation' [patent_app_type] => B2 [patent_app_number] => 09/726274 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7471 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622189.pdf [firstpage_image] =>[orig_patent_app_number] => 09726274 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726274
Method and system for low overhead spin lock instrumentation Nov 29, 2000 Issued
Array ( [id] => 1221687 [patent_doc_number] => 06708243 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Computer assembly with stub traces coupled to vias to add capacitance at the vias' [patent_app_type] => B1 [patent_app_number] => 09/724634 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1515 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708243.pdf [firstpage_image] =>[orig_patent_app_number] => 09724634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724634
Computer assembly with stub traces coupled to vias to add capacitance at the vias Nov 27, 2000 Issued
Array ( [id] => 7962291 [patent_doc_number] => 06681284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'System and method for providing a serial bus interface using distributed driver execution' [patent_app_type] => B1 [patent_app_number] => 09/723552 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6659 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681284.pdf [firstpage_image] =>[orig_patent_app_number] => 09723552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723552
System and method for providing a serial bus interface using distributed driver execution Nov 26, 2000 Issued
Array ( [id] => 1243082 [patent_doc_number] => 06684284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Control chipset, and data transaction method and signal transmission devices therefor' [patent_app_type] => B1 [patent_app_number] => 09/718811 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5903 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684284.pdf [firstpage_image] =>[orig_patent_app_number] => 09718811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/718811
Control chipset, and data transaction method and signal transmission devices therefor Nov 21, 2000 Issued
Array ( [id] => 7962297 [patent_doc_number] => 06681281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'System and method for implementing a multi-level interrupt scheme in a computer system' [patent_app_type] => B1 [patent_app_number] => 09/715606 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2873 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681281.pdf [firstpage_image] =>[orig_patent_app_number] => 09715606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715606
System and method for implementing a multi-level interrupt scheme in a computer system Nov 16, 2000 Issued
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