Search

Gopal C. Ray

Examiner (ID: 16225)

Most Active Art Unit
2781
Art Unit(s)
2307, 2781, 2305, 2111, 2181, 2787, 2308
Total Applications
1625
Issued Applications
1400
Pending Applications
56
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1364959 [patent_doc_number] => 06581117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Device and a method for the automatic control and administration of medical apparatus and installations' [patent_app_type] => B1 [patent_app_number] => 09/496300 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5287 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581117.pdf [firstpage_image] =>[orig_patent_app_number] => 09496300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496300
Device and a method for the automatic control and administration of medical apparatus and installations Feb 1, 2000 Issued
Array ( [id] => 4269923 [patent_doc_number] => 06223240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices' [patent_app_type] => 1 [patent_app_number] => 9/494477 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5282 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223240.pdf [firstpage_image] =>[orig_patent_app_number] => 494477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494477
Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices Jan 30, 2000 Issued
Array ( [id] => 1250223 [patent_doc_number] => 06675247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Loop formation eliminating apparatus of a serial bus system and method thereof' [patent_app_type] => B1 [patent_app_number] => 09/493035 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3069 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675247.pdf [firstpage_image] =>[orig_patent_app_number] => 09493035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493035
Loop formation eliminating apparatus of a serial bus system and method thereof Jan 27, 2000 Issued
Array ( [id] => 4422547 [patent_doc_number] => 06233691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Apparatus for reducing computer system power consumption' [patent_app_type] => 1 [patent_app_number] => 9/480101 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4225 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233691.pdf [firstpage_image] =>[orig_patent_app_number] => 480101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480101
Apparatus for reducing computer system power consumption Jan 9, 2000 Issued
Array ( [id] => 1602187 [patent_doc_number] => 06493778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Extensible time-sharing bus structure' [patent_app_type] => B1 [patent_app_number] => 09/475107 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2109 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493778.pdf [firstpage_image] =>[orig_patent_app_number] => 09475107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475107
Extensible time-sharing bus structure Dec 29, 1999 Issued
Array ( [id] => 1180841 [patent_doc_number] => 06754754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Apparatus and method for end of interrupt handling' [patent_app_type] => B1 [patent_app_number] => 09/475485 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3124 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754754.pdf [firstpage_image] =>[orig_patent_app_number] => 09475485 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475485
Apparatus and method for end of interrupt handling Dec 29, 1999 Issued
Array ( [id] => 1444045 [patent_doc_number] => 06496891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Device and method to emulate interrupts to provide PS/2 mouse and keyboard functionality for a USB mouse keyboard' [patent_app_type] => B1 [patent_app_number] => 09/475030 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7270 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496891.pdf [firstpage_image] =>[orig_patent_app_number] => 09475030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475030
Device and method to emulate interrupts to provide PS/2 mouse and keyboard functionality for a USB mouse keyboard Dec 29, 1999 Issued
Array ( [id] => 1456646 [patent_doc_number] => 06457079 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Communication apparatus with means for allocating alternate designation information to each function unit, and communication system with said two communication apparatuses' [patent_app_type] => B1 [patent_app_number] => 09/475251 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7898 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457079.pdf [firstpage_image] =>[orig_patent_app_number] => 09475251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475251
Communication apparatus with means for allocating alternate designation information to each function unit, and communication system with said two communication apparatuses Dec 29, 1999 Issued
Array ( [id] => 1297953 [patent_doc_number] => 06631430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Optimizations to receive packet status from fifo bus' [patent_app_type] => B1 [patent_app_number] => 09/473113 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2889 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631430.pdf [firstpage_image] =>[orig_patent_app_number] => 09473113 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473113
Optimizations to receive packet status from fifo bus Dec 27, 1999 Issued
Array ( [id] => 1521675 [patent_doc_number] => 06502156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Controlling I/O devices independently of a host processor' [patent_app_type] => B1 [patent_app_number] => 09/472502 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2243 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502156.pdf [firstpage_image] =>[orig_patent_app_number] => 09472502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472502
Controlling I/O devices independently of a host processor Dec 26, 1999 Issued
Array ( [id] => 1366144 [patent_doc_number] => 06584521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Scaleable bandwidth interconnect for simultaneous transfer of mixed pleisiochronous digital hierarchy (PDH) clients' [patent_app_type] => B1 [patent_app_number] => 09/472153 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10788 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584521.pdf [firstpage_image] =>[orig_patent_app_number] => 09472153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472153
Scaleable bandwidth interconnect for simultaneous transfer of mixed pleisiochronous digital hierarchy (PDH) clients Dec 26, 1999 Issued
Array ( [id] => 1318941 [patent_doc_number] => 06618780 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method and apparatus for controlling interrupt priority resolution' [patent_app_type] => B1 [patent_app_number] => 09/470763 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3447 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618780.pdf [firstpage_image] =>[orig_patent_app_number] => 09470763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470763
Method and apparatus for controlling interrupt priority resolution Dec 22, 1999 Issued
Array ( [id] => 1339036 [patent_doc_number] => 06601123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method and apparatus to control the signal development rate of a differential bus' [patent_app_type] => B1 [patent_app_number] => 09/471797 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3573 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601123.pdf [firstpage_image] =>[orig_patent_app_number] => 09471797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471797
Method and apparatus to control the signal development rate of a differential bus Dec 22, 1999 Issued
Array ( [id] => 7645916 [patent_doc_number] => 06477607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Duplexing structure of switching system processor and method thereof' [patent_app_type] => B1 [patent_app_number] => 09/470981 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3518 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477607.pdf [firstpage_image] =>[orig_patent_app_number] => 09470981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470981
Duplexing structure of switching system processor and method thereof Dec 22, 1999 Issued
Array ( [id] => 1584684 [patent_doc_number] => 06449674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Internal command signal generator and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/471486 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2592 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449674.pdf [firstpage_image] =>[orig_patent_app_number] => 09471486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471486
Internal command signal generator and method therefor Dec 22, 1999 Issued
Array ( [id] => 1416757 [patent_doc_number] => 06532509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Arbitrating command requests in a parallel multi-threaded processing system' [patent_app_type] => B1 [patent_app_number] => 09/470541 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5193 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532509.pdf [firstpage_image] =>[orig_patent_app_number] => 09470541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470541
Arbitrating command requests in a parallel multi-threaded processing system Dec 21, 1999 Issued
Array ( [id] => 1294848 [patent_doc_number] => 06640275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'System and method for data transfer between buses having different speeds' [patent_app_type] => B1 [patent_app_number] => 09/470076 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3443 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/640/06640275.pdf [firstpage_image] =>[orig_patent_app_number] => 09470076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470076
System and method for data transfer between buses having different speeds Dec 21, 1999 Issued
Array ( [id] => 4279651 [patent_doc_number] => 06205509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for improving interrupt response time' [patent_app_type] => 1 [patent_app_number] => 9/464263 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6898 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205509.pdf [firstpage_image] =>[orig_patent_app_number] => 464263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464263
Method for improving interrupt response time Dec 16, 1999 Issued
Array ( [id] => 1418501 [patent_doc_number] => 06546443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Concurrency-safe reader-writer lock with time out support' [patent_app_type] => B1 [patent_app_number] => 09/465239 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 15032 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546443.pdf [firstpage_image] =>[orig_patent_app_number] => 09465239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465239
Concurrency-safe reader-writer lock with time out support Dec 14, 1999 Issued
Array ( [id] => 1431858 [patent_doc_number] => 06516376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Command and control architecture for a video decoder and a host' [patent_app_type] => B1 [patent_app_number] => 09/449897 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4141 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516376.pdf [firstpage_image] =>[orig_patent_app_number] => 09449897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449897
Command and control architecture for a video decoder and a host Nov 29, 1999 Issued
Menu