Search

Gopal C. Ray

Examiner (ID: 16225)

Most Active Art Unit
2781
Art Unit(s)
2307, 2781, 2305, 2111, 2181, 2787, 2308
Total Applications
1625
Issued Applications
1400
Pending Applications
56
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1432370 [patent_doc_number] => 06505262 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Glitch protection and detection for strobed data' [patent_app_type] => B1 [patent_app_number] => 09/449627 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505262.pdf [firstpage_image] =>[orig_patent_app_number] => 09449627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449627
Glitch protection and detection for strobed data Nov 29, 1999 Issued
Array ( [id] => 1430951 [patent_doc_number] => 06507878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Bus snoop control circuit' [patent_app_type] => B1 [patent_app_number] => 09/449469 [patent_app_country] => US [patent_app_date] => 1999-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3584 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507878.pdf [firstpage_image] =>[orig_patent_app_number] => 09449469 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449469
Bus snoop control circuit Nov 28, 1999 Issued
Array ( [id] => 1521674 [patent_doc_number] => 06502155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Radio network and method of establishing time synchronization among a plurality of buses' [patent_app_type] => B1 [patent_app_number] => 09/449977 [patent_app_country] => US [patent_app_date] => 1999-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 12424 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502155.pdf [firstpage_image] =>[orig_patent_app_number] => 09449977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449977
Radio network and method of establishing time synchronization among a plurality of buses Nov 25, 1999 Issued
Array ( [id] => 1521670 [patent_doc_number] => 06502154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Bus bridging method and apparatus including use of read size indicators' [patent_app_type] => B1 [patent_app_number] => 09/449502 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4739 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502154.pdf [firstpage_image] =>[orig_patent_app_number] => 09449502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449502
Bus bridging method and apparatus including use of read size indicators Nov 23, 1999 Issued
Array ( [id] => 4374177 [patent_doc_number] => 06202161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Security control for computer power supply subsystem' [patent_app_type] => 1 [patent_app_number] => 9/448451 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5017 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202161.pdf [firstpage_image] =>[orig_patent_app_number] => 448451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448451
Security control for computer power supply subsystem Nov 23, 1999 Issued
Array ( [id] => 1297979 [patent_doc_number] => 06631434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Dynamic early indication system for a computer' [patent_app_type] => B1 [patent_app_number] => 09/440396 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12231 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631434.pdf [firstpage_image] =>[orig_patent_app_number] => 09440396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/440396
Dynamic early indication system for a computer Nov 14, 1999 Issued
Array ( [id] => 4323702 [patent_doc_number] => 06189064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Graphics display system with unified memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/437209 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 36790 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189064.pdf [firstpage_image] =>[orig_patent_app_number] => 437209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437209
Graphics display system with unified memory architecture Nov 8, 1999 Issued
Array ( [id] => 1431846 [patent_doc_number] => 06516368 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release' [patent_app_type] => B1 [patent_app_number] => 09/435928 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7345 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516368.pdf [firstpage_image] =>[orig_patent_app_number] => 09435928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435928
Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release Nov 8, 1999 Issued
Array ( [id] => 1533067 [patent_doc_number] => 06480915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release' [patent_app_type] => B1 [patent_app_number] => 09/436023 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6738 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480915.pdf [firstpage_image] =>[orig_patent_app_number] => 09436023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436023
Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release Nov 8, 1999 Issued
Array ( [id] => 4259644 [patent_doc_number] => 06092144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method and system for interrupt-responsive execution of communications protocols' [patent_app_type] => 1 [patent_app_number] => 9/436009 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6125 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092144.pdf [firstpage_image] =>[orig_patent_app_number] => 436009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436009
Method and system for interrupt-responsive execution of communications protocols Nov 8, 1999 Issued
Array ( [id] => 1471873 [patent_doc_number] => 06460101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Token manager for execution of global operations utilizing multiple tokens' [patent_app_type] => B1 [patent_app_number] => 09/435926 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8054 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460101.pdf [firstpage_image] =>[orig_patent_app_number] => 09435926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435926
Token manager for execution of global operations utilizing multiple tokens Nov 8, 1999 Issued
Array ( [id] => 1471870 [patent_doc_number] => 06460100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Bus snooper for SMP execution of global operations utilizing a single token with implied release' [patent_app_type] => B1 [patent_app_number] => 09/435929 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6702 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460100.pdf [firstpage_image] =>[orig_patent_app_number] => 09435929 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435929
Bus snooper for SMP execution of global operations utilizing a single token with implied release Nov 8, 1999 Issued
Array ( [id] => 1513180 [patent_doc_number] => 06442629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Bus protocol and token manager for execution of global operations utilizing a single token with multiple operations with explicit release' [patent_app_type] => B1 [patent_app_number] => 09/435924 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442629.pdf [firstpage_image] =>[orig_patent_app_number] => 09435924 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435924
Bus protocol and token manager for execution of global operations utilizing a single token with multiple operations with explicit release Nov 8, 1999 Issued
Array ( [id] => 1456670 [patent_doc_number] => 06457085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and system for data bus latency reduction using transfer size prediction for split bus designs' [patent_app_type] => B1 [patent_app_number] => 09/434764 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 15465 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457085.pdf [firstpage_image] =>[orig_patent_app_number] => 09434764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434764
Method and system for data bus latency reduction using transfer size prediction for split bus designs Nov 3, 1999 Issued
Array ( [id] => 1431856 [patent_doc_number] => 06516375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Peripheral component interconnect (PCI) configuration emulation for hub interface' [patent_app_type] => B1 [patent_app_number] => 09/433275 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 8709 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516375.pdf [firstpage_image] =>[orig_patent_app_number] => 09433275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433275
Peripheral component interconnect (PCI) configuration emulation for hub interface Nov 2, 1999 Issued
Array ( [id] => 1552780 [patent_doc_number] => 06446154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and mechanism for virtualizing legacy sideband signals in a hub interface architecture' [patent_app_type] => B1 [patent_app_number] => 09/433824 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9126 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446154.pdf [firstpage_image] =>[orig_patent_app_number] => 09433824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433824
Method and mechanism for virtualizing legacy sideband signals in a hub interface architecture Nov 2, 1999 Issued
Array ( [id] => 1109679 [patent_doc_number] => 06813663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method and apparatus for supporting and presenting multiple serial bus nodes using distinct configuration ROM images' [patent_app_type] => B1 [patent_app_number] => 09/432869 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4250 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813663.pdf [firstpage_image] =>[orig_patent_app_number] => 09432869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432869
Method and apparatus for supporting and presenting multiple serial bus nodes using distinct configuration ROM images Nov 1, 1999 Issued
Array ( [id] => 4193031 [patent_doc_number] => 06141764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method for initializing an electronic device using a dual-state power-on-reset circuit' [patent_app_type] => 1 [patent_app_number] => 9/427525 [patent_app_country] => US [patent_app_date] => 1999-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2715 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141764.pdf [firstpage_image] =>[orig_patent_app_number] => 427525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427525
Method for initializing an electronic device using a dual-state power-on-reset circuit Oct 25, 1999 Issued
Array ( [id] => 1505923 [patent_doc_number] => 06487619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Multiprocessor system that communicates through an internal bus using a network protocol' [patent_app_type] => B1 [patent_app_number] => 09/417643 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5176 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487619.pdf [firstpage_image] =>[orig_patent_app_number] => 09417643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417643
Multiprocessor system that communicates through an internal bus using a network protocol Oct 13, 1999 Issued
Array ( [id] => 1428846 [patent_doc_number] => 06513085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Link/transaction layer controller with integral microcontroller emulation' [patent_app_type] => B1 [patent_app_number] => 09/417453 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 10376 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513085.pdf [firstpage_image] =>[orig_patent_app_number] => 09417453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417453
Link/transaction layer controller with integral microcontroller emulation Oct 12, 1999 Issued
Menu