
Gopal C. Ray
Examiner (ID: 2012)
| Most Active Art Unit | 2781 |
| Art Unit(s) | 2305, 2308, 2307, 2781, 2111, 2787, 2181 |
| Total Applications | 1625 |
| Issued Applications | 1400 |
| Pending Applications | 56 |
| Abandoned Applications | 169 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1428846
[patent_doc_number] => 06513085
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-28
[patent_title] => 'Link/transaction layer controller with integral microcontroller emulation'
[patent_app_type] => B1
[patent_app_number] => 09/417453
[patent_app_country] => US
[patent_app_date] => 1999-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 10376
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/513/06513085.pdf
[firstpage_image] =>[orig_patent_app_number] => 09417453
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/417453 | Link/transaction layer controller with integral microcontroller emulation | Oct 12, 1999 | Issued |
Array
(
[id] => 7644150
[patent_doc_number] => 06473824
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-29
[patent_title] => 'Dynamic association of input/output device with application programs'
[patent_app_type] => B1
[patent_app_number] => 09/416834
[patent_app_country] => US
[patent_app_date] => 1999-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6553
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/473/06473824.pdf
[firstpage_image] =>[orig_patent_app_number] => 09416834
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/416834 | Dynamic association of input/output device with application programs | Oct 11, 1999 | Issued |
Array
(
[id] => 1381292
[patent_doc_number] => 06574693
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-06-03
[patent_title] => 'Method and apparatus for gating interrupts in a computing system'
[patent_app_type] => B1
[patent_app_number] => 09/416144
[patent_app_country] => US
[patent_app_date] => 1999-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7434
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/574/06574693.pdf
[firstpage_image] =>[orig_patent_app_number] => 09416144
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/416144 | Method and apparatus for gating interrupts in a computing system | Oct 10, 1999 | Issued |
Array
(
[id] => 4268885
[patent_doc_number] => 06138196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-24
[patent_title] => 'Communication system for providing digital data transfer, electronic equipment for transferring data using the communication system, and an interface control device'
[patent_app_type] => 1
[patent_app_number] => 9/414319
[patent_app_country] => US
[patent_app_date] => 1999-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 6289
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/138/06138196.pdf
[firstpage_image] =>[orig_patent_app_number] => 414319
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/414319 | Communication system for providing digital data transfer, electronic equipment for transferring data using the communication system, and an interface control device | Oct 6, 1999 | Issued |
Array
(
[id] => 4118016
[patent_doc_number] => 06098136
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Multiple bus system using a data transfer unit'
[patent_app_type] => 1
[patent_app_number] => 9/375356
[patent_app_country] => US
[patent_app_date] => 1999-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 7081
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/098/06098136.pdf
[firstpage_image] =>[orig_patent_app_number] => 375356
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/375356 | Multiple bus system using a data transfer unit | Aug 16, 1999 | Issued |
Array
(
[id] => 1513203
[patent_doc_number] => 06442637
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Expandable mobile computer system'
[patent_app_type] => B1
[patent_app_number] => 09/374058
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 3574
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/442/06442637.pdf
[firstpage_image] =>[orig_patent_app_number] => 09374058
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/374058 | Expandable mobile computer system | Aug 11, 1999 | Issued |
Array
(
[id] => 1540512
[patent_doc_number] => 06490642
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Locked read/write on separate address/data bus using write barrier'
[patent_app_type] => B1
[patent_app_number] => 09/373092
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 10645
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/490/06490642.pdf
[firstpage_image] =>[orig_patent_app_number] => 09373092
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373092 | Locked read/write on separate address/data bus using write barrier | Aug 11, 1999 | Issued |
Array
(
[id] => 1602182
[patent_doc_number] => 06493776
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-10
[patent_title] => 'Scalable on-chip system bus'
[patent_app_type] => B1
[patent_app_number] => 09/373091
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 11153
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/493/06493776.pdf
[firstpage_image] =>[orig_patent_app_number] => 09373091
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373091 | Scalable on-chip system bus | Aug 11, 1999 | Issued |
Array
(
[id] => 1533101
[patent_doc_number] => 06480922
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Computer software control and communication system and method'
[patent_app_type] => B1
[patent_app_number] => 09/373920
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3599
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/480/06480922.pdf
[firstpage_image] =>[orig_patent_app_number] => 09373920
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373920 | Computer software control and communication system and method | Aug 11, 1999 | Issued |
Array
(
[id] => 7962293
[patent_doc_number] => 06681283
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-20
[patent_title] => 'Coherent data apparatus for an on-chip split transaction system bus'
[patent_app_type] => B1
[patent_app_number] => 09/373094
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 10413
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/681/06681283.pdf
[firstpage_image] =>[orig_patent_app_number] => 09373094
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373094 | Coherent data apparatus for an on-chip split transaction system bus | Aug 11, 1999 | Issued |
Array
(
[id] => 1336947
[patent_doc_number] => 06604159
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-08-05
[patent_title] => 'Data release to reduce latency in on-chip system bus'
[patent_app_type] => B1
[patent_app_number] => 09/373093
[patent_app_country] => US
[patent_app_date] => 1999-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 9605
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/604/06604159.pdf
[firstpage_image] =>[orig_patent_app_number] => 09373093
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/373093 | Data release to reduce latency in on-chip system bus | Aug 11, 1999 | Issued |
Array
(
[id] => 1539345
[patent_doc_number] => 06412076
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Signal processing apparatus and image sensing apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/372437
[patent_app_country] => US
[patent_app_date] => 1999-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 26
[patent_no_of_words] => 10698
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/412/06412076.pdf
[firstpage_image] =>[orig_patent_app_number] => 09372437
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/372437 | Signal processing apparatus and image sensing apparatus | Aug 10, 1999 | Issued |
Array
(
[id] => 1513411
[patent_doc_number] => 06442702
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'On-vehicle computer having function of protecting vehicular battery'
[patent_app_type] => B1
[patent_app_number] => 09/370898
[patent_app_country] => US
[patent_app_date] => 1999-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 13960
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/442/06442702.pdf
[firstpage_image] =>[orig_patent_app_number] => 09370898
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/370898 | On-vehicle computer having function of protecting vehicular battery | Aug 9, 1999 | Issued |
Array
(
[id] => 1513405
[patent_doc_number] => 06442700
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Thermal control within systems having multiple CPU performance states'
[patent_app_type] => B1
[patent_app_number] => 09/371381
[patent_app_country] => US
[patent_app_date] => 1999-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 20842
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/442/06442700.pdf
[firstpage_image] =>[orig_patent_app_number] => 09371381
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/371381 | Thermal control within systems having multiple CPU performance states | Aug 9, 1999 | Issued |
Array
(
[id] => 1456886
[patent_doc_number] => 06457135
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'System and method for managing a plurality of processor performance states'
[patent_app_type] => B1
[patent_app_number] => 09/371268
[patent_app_country] => US
[patent_app_date] => 1999-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 14
[patent_no_of_words] => 18277
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/457/06457135.pdf
[firstpage_image] =>[orig_patent_app_number] => 09371268
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/371268 | System and method for managing a plurality of processor performance states | Aug 9, 1999 | Issued |
Array
(
[id] => 4238751
[patent_doc_number] => 06088753
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method'
[patent_app_type] => 1
[patent_app_number] => 9/365441
[patent_app_country] => US
[patent_app_date] => 1999-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 36809
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/088/06088753.pdf
[firstpage_image] =>[orig_patent_app_number] => 365441
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/365441 | Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method | Aug 1, 1999 | Issued |
Array
(
[id] => 1584980
[patent_doc_number] => 06449726
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Method, system, software, and signal for estimating battery life in a remote control device'
[patent_app_type] => B1
[patent_app_number] => 09/357792
[patent_app_country] => US
[patent_app_date] => 1999-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3974
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/449/06449726.pdf
[firstpage_image] =>[orig_patent_app_number] => 09357792
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/357792 | Method, system, software, and signal for estimating battery life in a remote control device | Jul 20, 1999 | Issued |
Array
(
[id] => 1601955
[patent_doc_number] => 06385684
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'Intelligent PC add-in board'
[patent_app_type] => B1
[patent_app_number] => 09/358190
[patent_app_country] => US
[patent_app_date] => 1999-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3360
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/385/06385684.pdf
[firstpage_image] =>[orig_patent_app_number] => 09358190
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/358190 | Intelligent PC add-in board | Jul 20, 1999 | Issued |
Array
(
[id] => 1533097
[patent_doc_number] => 06480921
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Reducing internal bus speed in a bus system without reducing readout rate'
[patent_app_type] => B1
[patent_app_number] => 09/359068
[patent_app_country] => US
[patent_app_date] => 1999-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2628
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/480/06480921.pdf
[firstpage_image] =>[orig_patent_app_number] => 09359068
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/359068 | Reducing internal bus speed in a bus system without reducing readout rate | Jul 20, 1999 | Issued |
Array
(
[id] => 7645920
[patent_doc_number] => 06477603
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Multiple PCI adapters within single PCI slot on an matax planar'
[patent_app_type] => B1
[patent_app_number] => 09/358106
[patent_app_country] => US
[patent_app_date] => 1999-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1615
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/477/06477603.pdf
[firstpage_image] =>[orig_patent_app_number] => 09358106
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/358106 | Multiple PCI adapters within single PCI slot on an matax planar | Jul 20, 1999 | Issued |