
Gopal C. Ray
Examiner (ID: 16225)
| Most Active Art Unit | 2781 |
| Art Unit(s) | 2307, 2781, 2305, 2111, 2181, 2787, 2308 |
| Total Applications | 1625 |
| Issued Applications | 1400 |
| Pending Applications | 56 |
| Abandoned Applications | 169 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4317626
[patent_doc_number] => 06185652
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Interrupt mechanism on NorthBay'
[patent_app_type] => 1
[patent_app_number] => 9/186043
[patent_app_country] => US
[patent_app_date] => 1998-11-03
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/185/06185652.pdf
[firstpage_image] =>[orig_patent_app_number] => 186043
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/186043 | Interrupt mechanism on NorthBay | Nov 2, 1998 | Issued |
Array
(
[id] => 4423681
[patent_doc_number] => 06311289
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[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'Explicit state copy in a fault tolerant system using a remote write operation'
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[patent_app_number] => 9/185474
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[patent_app_date] => 1998-11-03
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[pdf_file] => patents/06/311/06311289.pdf
[firstpage_image] =>[orig_patent_app_number] => 185474
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/185474 | Explicit state copy in a fault tolerant system using a remote write operation | Nov 2, 1998 | Issued |
Array
(
[id] => 1490241
[patent_doc_number] => 06367029
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'File server system tolerant to software and hardware failures'
[patent_app_type] => B1
[patent_app_number] => 09/185414
[patent_app_country] => US
[patent_app_date] => 1998-11-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/185414 | File server system tolerant to software and hardware failures | Nov 2, 1998 | Issued |
Array
(
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[patent_issue_date] => 2001-01-09
[patent_title] => 'Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem'
[patent_app_type] => 1
[patent_app_number] => 9/186042
[patent_app_country] => US
[patent_app_date] => 1998-11-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/186042 | Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem | Nov 2, 1998 | Issued |
Array
(
[id] => 4199513
[patent_doc_number] => 06038673
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[patent_issue_date] => 2000-03-14
[patent_title] => 'Computer system with power management scheme for DRAM devices'
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[patent_app_number] => 9/186290
[patent_app_country] => US
[patent_app_date] => 1998-11-03
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[firstpage_image] =>[orig_patent_app_number] => 186290
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/186290 | Computer system with power management scheme for DRAM devices | Nov 2, 1998 | Issued |
Array
(
[id] => 4281548
[patent_doc_number] => 06260162
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[patent_issue_date] => 2001-07-10
[patent_title] => 'Test mode programmable reset for a watchdog timer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/183915 | Test mode programmable reset for a watchdog timer | Oct 30, 1998 | Issued |
Array
(
[id] => 4402897
[patent_doc_number] => 06279126
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[patent_title] => 'Method for verifying that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically'
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Array
(
[id] => 1459981
[patent_doc_number] => 06463498
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[patent_issue_date] => 2002-10-08
[patent_title] => 'Transmission of FCP response in the same loop tenancy as the FCP data with minimization of inter-sequence gap'
[patent_app_type] => B1
[patent_app_number] => 09/183970
[patent_app_country] => US
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Array
(
[id] => 4178773
[patent_doc_number] => 06115768
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[patent_issue_date] => 2000-09-05
[patent_title] => 'System and method for controlling main memory employing pipeline-controlled bus'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182239 | System and method for controlling main memory employing pipeline-controlled bus | Oct 29, 1998 | Issued |
Array
(
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[patent_issue_date] => 2000-09-12
[patent_title] => 'Self regulating temperature/performance/voltage scheme for micros (X86)'
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[patent_app_number] => 9/183342
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Array
(
[id] => 4381926
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[patent_title] => 'Restoring checkpointed processes without restoring attributes of external data referenced by the processes'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/182725 | Restoring checkpointed processes without restoring attributes of external data referenced by the processes | Oct 28, 1998 | Issued |
Array
(
[id] => 4312852
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[patent_title] => 'Method for logical connection resynchronization'
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Array
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Array
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Array
(
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Array
(
[id] => 4373946
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Array
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Array
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Array
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Array
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