Search

Gopal C. Ray

Examiner (ID: 16225)

Most Active Art Unit
2781
Art Unit(s)
2307, 2781, 2305, 2111, 2181, 2787, 2308
Total Applications
1625
Issued Applications
1400
Pending Applications
56
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4317626 [patent_doc_number] => 06185652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Interrupt mechanism on NorthBay' [patent_app_type] => 1 [patent_app_number] => 9/186043 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8139 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185652.pdf [firstpage_image] =>[orig_patent_app_number] => 186043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186043
Interrupt mechanism on NorthBay Nov 2, 1998 Issued
Array ( [id] => 4423681 [patent_doc_number] => 06311289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Explicit state copy in a fault tolerant system using a remote write operation' [patent_app_type] => 1 [patent_app_number] => 9/185474 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7232 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311289.pdf [firstpage_image] =>[orig_patent_app_number] => 185474 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185474
Explicit state copy in a fault tolerant system using a remote write operation Nov 2, 1998 Issued
Array ( [id] => 1490241 [patent_doc_number] => 06367029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'File server system tolerant to software and hardware failures' [patent_app_type] => B1 [patent_app_number] => 09/185414 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7877 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/367/06367029.pdf [firstpage_image] =>[orig_patent_app_number] => 09185414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185414
File server system tolerant to software and hardware failures Nov 2, 1998 Issued
Array ( [id] => 4422185 [patent_doc_number] => 06173345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem' [patent_app_type] => 1 [patent_app_number] => 9/186042 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4503 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173345.pdf [firstpage_image] =>[orig_patent_app_number] => 186042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186042
Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem Nov 2, 1998 Issued
Array ( [id] => 4199513 [patent_doc_number] => 06038673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Computer system with power management scheme for DRAM devices' [patent_app_type] => 1 [patent_app_number] => 9/186290 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3960 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038673.pdf [firstpage_image] =>[orig_patent_app_number] => 186290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186290
Computer system with power management scheme for DRAM devices Nov 2, 1998 Issued
Array ( [id] => 4281548 [patent_doc_number] => 06260162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Test mode programmable reset for a watchdog timer' [patent_app_type] => 1 [patent_app_number] => 9/183915 [patent_app_country] => US [patent_app_date] => 1998-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6809 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260162.pdf [firstpage_image] =>[orig_patent_app_number] => 183915 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183915
Test mode programmable reset for a watchdog timer Oct 30, 1998 Issued
Array ( [id] => 4402897 [patent_doc_number] => 06279126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method for verifying that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically' [patent_app_type] => 1 [patent_app_number] => 9/183572 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2525 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279126.pdf [firstpage_image] =>[orig_patent_app_number] => 183572 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183572
Method for verifying that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically Oct 29, 1998 Issued
Array ( [id] => 1459981 [patent_doc_number] => 06463498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Transmission of FCP response in the same loop tenancy as the FCP data with minimization of inter-sequence gap' [patent_app_type] => B1 [patent_app_number] => 09/183970 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 15753 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463498.pdf [firstpage_image] =>[orig_patent_app_number] => 09183970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183970
Transmission of FCP response in the same loop tenancy as the FCP data with minimization of inter-sequence gap Oct 29, 1998 Issued
Array ( [id] => 4178773 [patent_doc_number] => 06115768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'System and method for controlling main memory employing pipeline-controlled bus' [patent_app_type] => 1 [patent_app_number] => 9/182239 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 16054 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115768.pdf [firstpage_image] =>[orig_patent_app_number] => 182239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182239
System and method for controlling main memory employing pipeline-controlled bus Oct 29, 1998 Issued
Array ( [id] => 4255597 [patent_doc_number] => 06119241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Self regulating temperature/performance/voltage scheme for micros (X86)' [patent_app_type] => 1 [patent_app_number] => 9/183342 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3368 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119241.pdf [firstpage_image] =>[orig_patent_app_number] => 183342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183342
Self regulating temperature/performance/voltage scheme for micros (X86) Oct 29, 1998 Issued
Array ( [id] => 4381926 [patent_doc_number] => 06256751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Restoring checkpointed processes without restoring attributes of external data referenced by the processes' [patent_app_type] => 1 [patent_app_number] => 9/182725 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4451 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256751.pdf [firstpage_image] =>[orig_patent_app_number] => 182725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182725
Restoring checkpointed processes without restoring attributes of external data referenced by the processes Oct 28, 1998 Issued
Array ( [id] => 4312852 [patent_doc_number] => 06237111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method for logical connection resynchronization' [patent_app_type] => 1 [patent_app_number] => 9/181753 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4573 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237111.pdf [firstpage_image] =>[orig_patent_app_number] => 181753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181753
Method for logical connection resynchronization Oct 28, 1998 Issued
Array ( [id] => 4424965 [patent_doc_number] => 06230283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Logical connection resynchronization' [patent_app_type] => 1 [patent_app_number] => 9/181705 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4703 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230283.pdf [firstpage_image] =>[orig_patent_app_number] => 181705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181705
Logical connection resynchronization Oct 28, 1998 Issued
Array ( [id] => 4333547 [patent_doc_number] => 06332200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Capturing and identifying a complete and consistent set of checkpoint files' [patent_app_type] => 1 [patent_app_number] => 9/182175 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6538 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332200.pdf [firstpage_image] =>[orig_patent_app_number] => 182175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182175
Capturing and identifying a complete and consistent set of checkpoint files Oct 28, 1998 Issued
Array ( [id] => 4389065 [patent_doc_number] => 06275958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Fault detection in a redundant power converter' [patent_app_type] => 1 [patent_app_number] => 9/181498 [patent_app_country] => US [patent_app_date] => 1998-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275958.pdf [firstpage_image] =>[orig_patent_app_number] => 181498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181498
Fault detection in a redundant power converter Oct 27, 1998 Issued
Array ( [id] => 4373946 [patent_doc_number] => 06175887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Deterministic arbitration of a serial bus using arbitration addresses' [patent_app_type] => 1 [patent_app_number] => 9/176298 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4091 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175887.pdf [firstpage_image] =>[orig_patent_app_number] => 176298 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176298
Deterministic arbitration of a serial bus using arbitration addresses Oct 20, 1998 Issued
Array ( [id] => 4373976 [patent_doc_number] => 06175889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Apparatus, method and system for a computer CPU and memory to high speed peripheral interconnect bridge having a plurality of physical buses with a single logical bus number' [patent_app_type] => 1 [patent_app_number] => 9/177441 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 15594 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175889.pdf [firstpage_image] =>[orig_patent_app_number] => 177441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/177441
Apparatus, method and system for a computer CPU and memory to high speed peripheral interconnect bridge having a plurality of physical buses with a single logical bus number Oct 20, 1998 Issued
Array ( [id] => 4259627 [patent_doc_number] => 06092143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Mechanism for synchronizing service of interrupts by a plurality of data processors' [patent_app_type] => 1 [patent_app_number] => 9/175709 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4240 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092143.pdf [firstpage_image] =>[orig_patent_app_number] => 175709 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175709
Mechanism for synchronizing service of interrupts by a plurality of data processors Oct 19, 1998 Issued
Array ( [id] => 4178992 [patent_doc_number] => 06115780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Interrupt steering circuit for PCI bus' [patent_app_type] => 1 [patent_app_number] => 9/175275 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3015 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115780.pdf [firstpage_image] =>[orig_patent_app_number] => 175275 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175275
Interrupt steering circuit for PCI bus Oct 19, 1998 Issued
Array ( [id] => 7634955 [patent_doc_number] => 06381711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method and apparatus for unified, pre-addressed, context-sensitive reporting' [patent_app_type] => B1 [patent_app_number] => 09/175841 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3572 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381711.pdf [firstpage_image] =>[orig_patent_app_number] => 09175841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175841
Method and apparatus for unified, pre-addressed, context-sensitive reporting Oct 19, 1998 Issued
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