Gopal C. Ray

Array ( [id] => 4256564 [patent_doc_number] => 06081848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Striping packets of data across multiple virtual channels' [patent_app_type] => 1 [patent_app_number] => 9/134737 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2338 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081848.pdf [firstpage_image] =>[orig_patent_app_number] => 134737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4160156 [patent_doc_number] => 06061745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'BBS one BIOS image multicard support' [patent_app_type] => 1 [patent_app_number] => 9/133736 [patent_app_country] => US [patent_app_date] => 1998-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4604 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061745.pdf [firstpage_image] =>[orig_patent_app_number] => 133736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4323485 [patent_doc_number] => 06189049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method for operating processor with internal register for peripheral status' [patent_app_type] => 1 [patent_app_number] => 9/131497 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4475 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189049.pdf [firstpage_image] =>[orig_patent_app_number] => 131497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4421827 [patent_doc_number] => 06233627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Processor with internal register for peripheral status' [patent_app_type] => 1 [patent_app_number] => 9/131446 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4477 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233627.pdf [firstpage_image] =>[orig_patent_app_number] => 131446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4375928 [patent_doc_number] => 06219720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Core logic unit with internal register for peripheral status' [patent_app_type] => 1 [patent_app_number] => 9/131447 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4294 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219720.pdf [firstpage_image] =>[orig_patent_app_number] => 131447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317275 [patent_doc_number] => 06185627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Analog and digital audio auto sense' [patent_app_type] => 1 [patent_app_number] => 9/131543 [patent_app_country] => US [patent_app_date] => 1998-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6039 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185627.pdf [firstpage_image] =>[orig_patent_app_number] => 131543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4192997 [patent_doc_number] => 06141762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Power reduction in a multiprocessor digital signal processor based on processor load' [patent_app_type] => 1 [patent_app_number] => 9/128030 [patent_app_country] => US [patent_app_date] => 1998-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3905 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141762.pdf [firstpage_image] =>[orig_patent_app_number] => 128030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4118561 [patent_doc_number] => 06098174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Power control circuitry for use in a computer system and systems using the same' [patent_app_type] => 1 [patent_app_number] => 9/128299 [patent_app_country] => US [patent_app_date] => 1998-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4240 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098174.pdf [firstpage_image] =>[orig_patent_app_number] => 128299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4225622 [patent_doc_number] => 06029218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Data transfer method and data transfer device' [patent_app_type] => 1 [patent_app_number] => 9/122062 [patent_app_country] => US [patent_app_date] => 1998-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 47 [patent_no_of_words] => 4216 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029218.pdf [firstpage_image] =>[orig_patent_app_number] => 122062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156542 [patent_doc_number] => 06122750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Apparatus for, and method of, isolating hardware and power source problems' [patent_app_type] => 1 [patent_app_number] => 9/119776 [patent_app_country] => US [patent_app_date] => 1998-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 3908 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122750.pdf [firstpage_image] =>[orig_patent_app_number] => 119776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4279550 [patent_doc_number] => 06205503 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for the hot swap and add of input/output platforms and devices' [patent_app_type] => 1 [patent_app_number] => 9/118716 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 11660 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205503.pdf [firstpage_image] =>[orig_patent_app_number] => 118716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269815 [patent_doc_number] => 06223234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Apparatus for the hot swap and add of input/output platforms and devices' [patent_app_type] => 1 [patent_app_number] => 9/118219 [patent_app_country] => US [patent_app_date] => 1998-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 12156 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223234.pdf [firstpage_image] =>[orig_patent_app_number] => 118219 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4269881 [patent_doc_number] => 06223237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Expandable communications bus' [patent_app_type] => 1 [patent_app_number] => 9/111500 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7049 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223237.pdf [firstpage_image] =>[orig_patent_app_number] => 111500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4126527 [patent_doc_number] => 06058442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Computer system having reversible bus connectors' [patent_app_type] => 1 [patent_app_number] => 9/104737 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3747 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058442.pdf [firstpage_image] =>[orig_patent_app_number] => 104737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155676 [patent_doc_number] => 06122697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'System for extending the width of a data bus' [patent_app_type] => 1 [patent_app_number] => 9/100890 [patent_app_country] => US [patent_app_date] => 1998-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5747 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122697.pdf [firstpage_image] =>[orig_patent_app_number] => 100890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426885 [patent_doc_number] => 06195720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Device and method for communication between asynchronous computer buses using an adapter' [patent_app_type] => 1 [patent_app_number] => 9/100101 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11274 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195720.pdf [firstpage_image] =>[orig_patent_app_number] => 100101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4370812 [patent_doc_number] => 06216186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Modular computer system including compatibility evaluation logic' [patent_app_type] => 1 [patent_app_number] => 9/097469 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5203 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216186.pdf [firstpage_image] =>[orig_patent_app_number] => 097469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4260039 [patent_doc_number] => 06167477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Computer system bridge employing a resource control mechanism with programmable registers to control resource allocation' [patent_app_type] => 1 [patent_app_number] => 9/094847 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 15052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/167/06167477.pdf [firstpage_image] =>[orig_patent_app_number] => 094847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257374 [patent_doc_number] => 06145043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Boolean and movement accelerator' [patent_app_type] => 1 [patent_app_number] => 9/092101 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4320 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145043.pdf [firstpage_image] =>[orig_patent_app_number] => 092101 [rel_patent_id] =>[rel_patent_doc_number] =>)