Search

Gopal C. Ray

Examiner (ID: 16225)

Most Active Art Unit
2781
Art Unit(s)
2307, 2781, 2305, 2111, 2181, 2787, 2308
Total Applications
1625
Issued Applications
1400
Pending Applications
56
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4194579 [patent_doc_number] => 06085265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'System for handling an asynchronous interrupt a universal serial bus device' [patent_app_type] => 1 [patent_app_number] => 9/004835 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7390 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085265.pdf [firstpage_image] =>[orig_patent_app_number] => 004835 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004835
System for handling an asynchronous interrupt a universal serial bus device Jan 8, 1998 Issued
Array ( [id] => 4161895 [patent_doc_number] => 06032202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Home audio/video network with two level device control' [patent_app_type] => 1 [patent_app_number] => 9/003119 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 16804 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032202.pdf [firstpage_image] =>[orig_patent_app_number] => 003119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003119
Home audio/video network with two level device control Jan 5, 1998 Issued
Array ( [id] => 4223471 [patent_doc_number] => 06078966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Switching means for directly controlling operation of data storage devices, data storage/reproducing devices, and data reproducing devices' [patent_app_type] => 1 [patent_app_number] => 9/002945 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4232 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078966.pdf [firstpage_image] =>[orig_patent_app_number] => 002945 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002945
Switching means for directly controlling operation of data storage devices, data storage/reproducing devices, and data reproducing devices Jan 4, 1998 Issued
Array ( [id] => 4426602 [patent_doc_number] => 06178476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Data communication interface including an integrated data processor and serial memory device' [patent_app_type] => 1 [patent_app_number] => 9/002638 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3158 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178476.pdf [firstpage_image] =>[orig_patent_app_number] => 002638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002638
Data communication interface including an integrated data processor and serial memory device Jan 4, 1998 Issued
Array ( [id] => 3932677 [patent_doc_number] => 06003104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'High speed modular internal microprocessor bus system' [patent_app_type] => 1 [patent_app_number] => 9/002014 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6009 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003104.pdf [firstpage_image] =>[orig_patent_app_number] => 002014 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002014
High speed modular internal microprocessor bus system Dec 30, 1997 Issued
Array ( [id] => 3932648 [patent_doc_number] => 06003102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Apparatus and method for arbitrating transactions requiring multiple addresses' [patent_app_type] => 1 [patent_app_number] => 9/001451 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6177 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003102.pdf [firstpage_image] =>[orig_patent_app_number] => 001451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001451
Apparatus and method for arbitrating transactions requiring multiple addresses Dec 30, 1997 Issued
Array ( [id] => 4423574 [patent_doc_number] => 06240475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Timer based arbitrations scheme for a PCI multi-function device' [patent_app_type] => 1 [patent_app_number] => 9/001245 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3321 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240475.pdf [firstpage_image] =>[orig_patent_app_number] => 001245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001245
Timer based arbitrations scheme for a PCI multi-function device Dec 29, 1997 Issued
Array ( [id] => 3965972 [patent_doc_number] => 05956516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals' [patent_app_type] => 1 [patent_app_number] => 8/997103 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4455 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956516.pdf [firstpage_image] =>[orig_patent_app_number] => 997103 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997103
Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals Dec 22, 1997 Issued
Array ( [id] => 4022651 [patent_doc_number] => 05987615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Programmable load transient compensator for reducing the transient response time to a load capable of operating at multiple power consumption levels' [patent_app_type] => 1 [patent_app_number] => 8/995503 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3789 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987615.pdf [firstpage_image] =>[orig_patent_app_number] => 995503 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995503
Programmable load transient compensator for reducing the transient response time to a load capable of operating at multiple power consumption levels Dec 21, 1997 Issued
Array ( [id] => 4021735 [patent_doc_number] => 05987555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Dynamic delayed transaction discard counter in a bus bridge of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/995386 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 14217 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987555.pdf [firstpage_image] =>[orig_patent_app_number] => 995386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995386
Dynamic delayed transaction discard counter in a bus bridge of a computer system Dec 21, 1997 Issued
Array ( [id] => 4121828 [patent_doc_number] => 06052751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Method and apparatus for changing the number of access slots into a memory' [patent_app_type] => 1 [patent_app_number] => 8/992814 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 17233 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052751.pdf [firstpage_image] =>[orig_patent_app_number] => 992814 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992814
Method and apparatus for changing the number of access slots into a memory Dec 17, 1997 Issued
Array ( [id] => 4133471 [patent_doc_number] => 06047379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Information bus regenerator' [patent_app_type] => 1 [patent_app_number] => 8/991993 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 9 [patent_no_of_words] => 3235 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047379.pdf [firstpage_image] =>[orig_patent_app_number] => 991993 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991993
Information bus regenerator Dec 16, 1997 Issued
Array ( [id] => 3915955 [patent_doc_number] => 05951663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method and apparatus for tracking bus transactions' [patent_app_type] => 1 [patent_app_number] => 8/992609 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3333 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951663.pdf [firstpage_image] =>[orig_patent_app_number] => 992609 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992609
Method and apparatus for tracking bus transactions Dec 16, 1997 Issued
Array ( [id] => 4088591 [patent_doc_number] => 06070220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Jump code generator, interrupt program selection system, interruption program selection method, and computer with the function' [patent_app_type] => 1 [patent_app_number] => 8/987211 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4961 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070220.pdf [firstpage_image] =>[orig_patent_app_number] => 987211 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987211
Jump code generator, interrupt program selection system, interruption program selection method, and computer with the function Dec 8, 1997 Issued
Array ( [id] => 3967822 [patent_doc_number] => 05983354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method and apparatus for indication when a bus master is communicating with memory' [patent_app_type] => 1 [patent_app_number] => 8/984319 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983354.pdf [firstpage_image] =>[orig_patent_app_number] => 984319 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984319
Method and apparatus for indication when a bus master is communicating with memory Dec 2, 1997 Issued
Array ( [id] => 3970263 [patent_doc_number] => 05991837 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Reverse oriented processor configuration' [patent_app_type] => 1 [patent_app_number] => 8/982573 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3822 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991837.pdf [firstpage_image] =>[orig_patent_app_number] => 982573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982573
Reverse oriented processor configuration Dec 1, 1997 Issued
Array ( [id] => 4177421 [patent_doc_number] => 06108734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method and apparatus for a relaxed bus protocol using heuristics and higher level supervision' [patent_app_type] => 1 [patent_app_number] => 8/982080 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1853 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108734.pdf [firstpage_image] =>[orig_patent_app_number] => 982080 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982080
Method and apparatus for a relaxed bus protocol using heuristics and higher level supervision Nov 30, 1997 Issued
Array ( [id] => 3968989 [patent_doc_number] => 05948088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Bus system providing dynamic control of pipeline depth for a multi-agent computer' [patent_app_type] => 1 [patent_app_number] => 8/979740 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5216 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948088.pdf [firstpage_image] =>[orig_patent_app_number] => 979740 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979740
Bus system providing dynamic control of pipeline depth for a multi-agent computer Nov 25, 1997 Issued
Array ( [id] => 3915998 [patent_doc_number] => 05951666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Bus system having both serial and parallel busses' [patent_app_type] => 1 [patent_app_number] => 8/976758 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5260 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951666.pdf [firstpage_image] =>[orig_patent_app_number] => 976758 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976758
Bus system having both serial and parallel busses Nov 23, 1997 Issued
Array ( [id] => 3974822 [patent_doc_number] => 05937200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Using firmware to enhance the functionality of a controller' [patent_app_type] => 1 [patent_app_number] => 8/975557 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6164 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937200.pdf [firstpage_image] =>[orig_patent_app_number] => 975557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975557
Using firmware to enhance the functionality of a controller Nov 20, 1997 Issued
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