Search

Gopal C. Ray

Examiner (ID: 2012)

Most Active Art Unit
2781
Art Unit(s)
2305, 2308, 2307, 2781, 2111, 2787, 2181
Total Applications
1625
Issued Applications
1400
Pending Applications
56
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3968851 [patent_doc_number] => 05948078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Assigned device numbers to units connected to a bus' [patent_app_type] => 1 [patent_app_number] => 8/966074 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4263 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948078.pdf [firstpage_image] =>[orig_patent_app_number] => 966074 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966074
Assigned device numbers to units connected to a bus Nov 6, 1997 Issued
Array ( [id] => 4020833 [patent_doc_number] => 05987495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method and apparatus for fully restoring a program context following an interrupt' [patent_app_type] => 1 [patent_app_number] => 8/966374 [patent_app_country] => US [patent_app_date] => 1997-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6412 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987495.pdf [firstpage_image] =>[orig_patent_app_number] => 966374 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/966374
Method and apparatus for fully restoring a program context following an interrupt Nov 6, 1997 Issued
Array ( [id] => 3997042 [patent_doc_number] => 05961619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method and apparatus for automatic activation of bus termination on a fast ethernet repeater stack' [patent_app_type] => 1 [patent_app_number] => 8/965330 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961619.pdf [firstpage_image] =>[orig_patent_app_number] => 965330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965330
Method and apparatus for automatic activation of bus termination on a fast ethernet repeater stack Nov 5, 1997 Issued
Array ( [id] => 4151406 [patent_doc_number] => 06035352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Computerized pager for storing and managing information' [patent_app_type] => 1 [patent_app_number] => 8/961677 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1854 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035352.pdf [firstpage_image] =>[orig_patent_app_number] => 961677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/961677
Computerized pager for storing and managing information Oct 30, 1997 Issued
Array ( [id] => 3968837 [patent_doc_number] => 05948077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Device identification with analog signal level' [patent_app_type] => 1 [patent_app_number] => 8/960506 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2620 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948077.pdf [firstpage_image] =>[orig_patent_app_number] => 960506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960506
Device identification with analog signal level Oct 28, 1997 Issued
Array ( [id] => 4040225 [patent_doc_number] => 05908468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Data transfer network on a chip utilizing a multiple traffic circle topology' [patent_app_type] => 1 [patent_app_number] => 8/957093 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/908/05908468.pdf [firstpage_image] =>[orig_patent_app_number] => 957093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957093
Data transfer network on a chip utilizing a multiple traffic circle topology Oct 23, 1997 Issued
Array ( [id] => 4177473 [patent_doc_number] => 06108737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/957097 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11579 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108737.pdf [firstpage_image] =>[orig_patent_app_number] => 957097 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957097
Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system Oct 23, 1997 Issued
Array ( [id] => 3951304 [patent_doc_number] => 05940599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Data processor' [patent_app_type] => 1 [patent_app_number] => 8/957160 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4467 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940599.pdf [firstpage_image] =>[orig_patent_app_number] => 957160 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957160
Data processor Oct 23, 1997 Issued
Array ( [id] => 3997082 [patent_doc_number] => 05961622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'System and method for recovering a microprocessor from a locked bus state' [patent_app_type] => 1 [patent_app_number] => 8/956966 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4152 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961622.pdf [firstpage_image] =>[orig_patent_app_number] => 956966 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956966
System and method for recovering a microprocessor from a locked bus state Oct 22, 1997 Issued
Array ( [id] => 4025991 [patent_doc_number] => 05941967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Unit for arbitration of access to a bus of a multiprocessor system with multiprocessor system for access to a plurality of shared resources, with temporary masking of pseudo random duration of access requests for the execution of access retry' [patent_app_type] => 1 [patent_app_number] => 8/956218 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7325 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941967.pdf [firstpage_image] =>[orig_patent_app_number] => 956218 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956218
Unit for arbitration of access to a bus of a multiprocessor system with multiprocessor system for access to a plurality of shared resources, with temporary masking of pseudo random duration of access requests for the execution of access retry Oct 21, 1997 Issued
Array ( [id] => 4100176 [patent_doc_number] => 06018741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method and system for managing objects in a dynamic inheritance tree' [patent_app_type] => 1 [patent_app_number] => 8/955101 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5785 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/018/06018741.pdf [firstpage_image] =>[orig_patent_app_number] => 955101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955101
Method and system for managing objects in a dynamic inheritance tree Oct 21, 1997 Issued
Array ( [id] => 4026108 [patent_doc_number] => 05941976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Interrupt request deassertion interlock mechanism' [patent_app_type] => 1 [patent_app_number] => 8/955309 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9699 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941976.pdf [firstpage_image] =>[orig_patent_app_number] => 955309 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955309
Interrupt request deassertion interlock mechanism Oct 19, 1997 Issued
Array ( [id] => 3877772 [patent_doc_number] => 05796961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Heuristic bus access arbiter' [patent_app_type] => 1 [patent_app_number] => 8/954617 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2912 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796961.pdf [firstpage_image] =>[orig_patent_app_number] => 954617 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954617
Heuristic bus access arbiter Oct 19, 1997 Issued
Array ( [id] => 4254680 [patent_doc_number] => 06119181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures' [patent_app_type] => 1 [patent_app_number] => 8/947254 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 6389 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119181.pdf [firstpage_image] =>[orig_patent_app_number] => 947254 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/947254
I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures Oct 7, 1997 Issued
Array ( [id] => 3918570 [patent_doc_number] => 05898843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'System and method for controlling device which is present in media console and system unit of a split computer system' [patent_app_type] => 1 [patent_app_number] => 8/954996 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11023 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898843.pdf [firstpage_image] =>[orig_patent_app_number] => 954996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954996
System and method for controlling device which is present in media console and system unit of a split computer system Oct 7, 1997 Issued
Array ( [id] => 3969058 [patent_doc_number] => 05948092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Local bus IDE architecture for a split computer system' [patent_app_type] => 1 [patent_app_number] => 8/946407 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10800 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948092.pdf [firstpage_image] =>[orig_patent_app_number] => 946407 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946407
Local bus IDE architecture for a split computer system Oct 6, 1997 Issued
Array ( [id] => 4236796 [patent_doc_number] => 06041415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Field bus arrangement having independent power circuits and control circuits' [patent_app_type] => 1 [patent_app_number] => 8/946400 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1661 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041415.pdf [firstpage_image] =>[orig_patent_app_number] => 946400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946400
Field bus arrangement having independent power circuits and control circuits Oct 6, 1997 Issued
Array ( [id] => 4254801 [patent_doc_number] => 06119189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Bus master transactions on a low pin count bus' [patent_app_type] => 1 [patent_app_number] => 8/936319 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7595 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119189.pdf [firstpage_image] =>[orig_patent_app_number] => 936319 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/936319
Bus master transactions on a low pin count bus Sep 23, 1997 Issued
Array ( [id] => 3974277 [patent_doc_number] => 05901299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method and apparatus for transferring data between buses having differing ordering policies' [patent_app_type] => 1 [patent_app_number] => 8/934413 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 16598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901299.pdf [firstpage_image] =>[orig_patent_app_number] => 934413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934413
Method and apparatus for transferring data between buses having differing ordering policies Sep 18, 1997 Issued
Array ( [id] => 4008565 [patent_doc_number] => 05892956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Serial bus for transmitting interrupt information in a multiprocessing system' [patent_app_type] => 1 [patent_app_number] => 8/934261 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6313 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892956.pdf [firstpage_image] =>[orig_patent_app_number] => 934261 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934261
Serial bus for transmitting interrupt information in a multiprocessing system Sep 18, 1997 Issued
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