
Gopal C. Ray
Examiner (ID: 16225)
| Most Active Art Unit | 2781 |
| Art Unit(s) | 2307, 2781, 2305, 2111, 2181, 2787, 2308 |
| Total Applications | 1625 |
| Issued Applications | 1400 |
| Pending Applications | 56 |
| Abandoned Applications | 169 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3974277
[patent_doc_number] => 05901299
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Method and apparatus for transferring data between buses having differing ordering policies'
[patent_app_type] => 1
[patent_app_number] => 8/934413
[patent_app_country] => US
[patent_app_date] => 1997-09-19
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[pdf_file] => patents/05/901/05901299.pdf
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Array
(
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[patent_doc_number] => 05913044
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[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Method and system for simultaneous variable-width bus access in a multiprocessor system'
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Array
(
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[patent_issue_date] => 2000-04-25
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Array
(
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[patent_issue_date] => 1999-07-27
[patent_title] => 'Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access'
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Array
(
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[patent_title] => 'Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access'
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Array
(
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[patent_issue_date] => 1999-09-21
[patent_title] => 'Method for configuring a computer-based system with a configuration card'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/932079 | Method for configuring a computer-based system with a configuration card | Sep 16, 1997 | Issued |
Array
(
[id] => 3970032
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[patent_issue_date] => 1999-09-28
[patent_title] => 'Circuit for arbitrating interrupts with programmable priority levels'
[patent_app_type] => 1
[patent_app_number] => 8/925342
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/925342 | Circuit for arbitrating interrupts with programmable priority levels | Sep 7, 1997 | Issued |
Array
(
[id] => 3779406
[patent_doc_number] => 05845142
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[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Portable terminal to control communication based on residual battery capacity'
[patent_app_type] => 1
[patent_app_number] => 8/921337
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[patent_app_date] => 1997-08-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/921337 | Portable terminal to control communication based on residual battery capacity | Aug 28, 1997 | Issued |
Array
(
[id] => 3997017
[patent_doc_number] => 05961617
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[patent_issue_date] => 1999-10-05
[patent_title] => 'System and technique for reducing power consumed by a data transfer operations during periods of update inactivity'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/914846 | System and technique for reducing power consumed by a data transfer operations during periods of update inactivity | Aug 17, 1997 | Issued |
Array
(
[id] => 4057289
[patent_doc_number] => 05909584
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[patent_issue_date] => 1999-06-01
[patent_title] => 'Power interlock with fault indicators for computer system'
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[patent_app_number] => 8/911250
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Array
(
[id] => 3993215
[patent_doc_number] => 05918059
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[patent_title] => 'Method and apparatus for responding to actuation of a power supply switch for a computing system'
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Array
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Array
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Array
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Array
(
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Array
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Array
(
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Array
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Array
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Array
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