Search

Gopal C. Ray

Examiner (ID: 16225)

Most Active Art Unit
2781
Art Unit(s)
2307, 2781, 2305, 2111, 2181, 2787, 2308
Total Applications
1625
Issued Applications
1400
Pending Applications
56
Abandoned Applications
169

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3974277 [patent_doc_number] => 05901299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method and apparatus for transferring data between buses having differing ordering policies' [patent_app_type] => 1 [patent_app_number] => 8/934413 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 16598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901299.pdf [firstpage_image] =>[orig_patent_app_number] => 934413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934413
Method and apparatus for transferring data between buses having differing ordering policies Sep 18, 1997 Issued
Array ( [id] => 4057639 [patent_doc_number] => 05913044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method and system for simultaneous variable-width bus access in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/933154 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3597 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913044.pdf [firstpage_image] =>[orig_patent_app_number] => 933154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933154
Method and system for simultaneous variable-width bus access in a multiprocessor system Sep 17, 1997 Issued
Array ( [id] => 4099718 [patent_doc_number] => 06055595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Apparatus and method for starting and terminating an application program' [patent_app_type] => 1 [patent_app_number] => 8/933098 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 6644 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055595.pdf [firstpage_image] =>[orig_patent_app_number] => 933098 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933098
Apparatus and method for starting and terminating an application program Sep 17, 1997 Issued
Array ( [id] => 3955097 [patent_doc_number] => 05930484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access' [patent_app_type] => 1 [patent_app_number] => 8/933156 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3603 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930484.pdf [firstpage_image] =>[orig_patent_app_number] => 933156 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933156
Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access Sep 17, 1997 Issued
Array ( [id] => 3974211 [patent_doc_number] => 05901294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access' [patent_app_type] => 1 [patent_app_number] => 8/933155 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3616 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901294.pdf [firstpage_image] =>[orig_patent_app_number] => 933155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933155
Method and system for bus arbitration in a multiprocessor system utilizing simultaneous variable-width bus access Sep 17, 1997 Issued
Array ( [id] => 3939825 [patent_doc_number] => 05954808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method for configuring a computer-based system with a configuration card' [patent_app_type] => 1 [patent_app_number] => 8/932079 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2784 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954808.pdf [firstpage_image] =>[orig_patent_app_number] => 932079 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932079
Method for configuring a computer-based system with a configuration card Sep 16, 1997 Issued
Array ( [id] => 3970032 [patent_doc_number] => 05958036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Circuit for arbitrating interrupts with programmable priority levels' [patent_app_type] => 1 [patent_app_number] => 8/925342 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5263 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958036.pdf [firstpage_image] =>[orig_patent_app_number] => 925342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925342
Circuit for arbitrating interrupts with programmable priority levels Sep 7, 1997 Issued
Array ( [id] => 3779406 [patent_doc_number] => 05845142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Portable terminal to control communication based on residual battery capacity' [patent_app_type] => 1 [patent_app_number] => 8/921337 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4640 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845142.pdf [firstpage_image] =>[orig_patent_app_number] => 921337 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921337
Portable terminal to control communication based on residual battery capacity Aug 28, 1997 Issued
Array ( [id] => 3997017 [patent_doc_number] => 05961617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'System and technique for reducing power consumed by a data transfer operations during periods of update inactivity' [patent_app_type] => 1 [patent_app_number] => 8/914846 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6533 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961617.pdf [firstpage_image] =>[orig_patent_app_number] => 914846 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914846
System and technique for reducing power consumed by a data transfer operations during periods of update inactivity Aug 17, 1997 Issued
Array ( [id] => 4057289 [patent_doc_number] => 05909584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Power interlock with fault indicators for computer system' [patent_app_type] => 1 [patent_app_number] => 8/911250 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4456 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909584.pdf [firstpage_image] =>[orig_patent_app_number] => 911250 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911250
Power interlock with fault indicators for computer system Aug 14, 1997 Issued
Array ( [id] => 3993215 [patent_doc_number] => 05918059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method and apparatus for responding to actuation of a power supply switch for a computing system' [patent_app_type] => 1 [patent_app_number] => 8/911648 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5646 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918059.pdf [firstpage_image] =>[orig_patent_app_number] => 911648 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911648
Method and apparatus for responding to actuation of a power supply switch for a computing system Aug 14, 1997 Issued
Array ( [id] => 3915913 [patent_doc_number] => 05951661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Bus protocol violation monitor systems and methods' [patent_app_type] => 1 [patent_app_number] => 8/911248 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7338 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951661.pdf [firstpage_image] =>[orig_patent_app_number] => 911248 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911248
Bus protocol violation monitor systems and methods Aug 14, 1997 Issued
Array ( [id] => 4057218 [patent_doc_number] => 05875307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method and apparatus to enable docking/undocking of a powered-on bus to a docking station' [patent_app_type] => 1 [patent_app_number] => 8/911537 [patent_app_country] => US [patent_app_date] => 1997-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3515 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875307.pdf [firstpage_image] =>[orig_patent_app_number] => 911537 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911537
Method and apparatus to enable docking/undocking of a powered-on bus to a docking station Aug 13, 1997 Issued
Array ( [id] => 3779271 [patent_doc_number] => 05845132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Computer system power management interconnection circuitry, system and methods' [patent_app_type] => 1 [patent_app_number] => 8/910862 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 79 [patent_no_of_words] => 92456 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845132.pdf [firstpage_image] =>[orig_patent_app_number] => 910862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910862
Computer system power management interconnection circuitry, system and methods Aug 12, 1997 Issued
Array ( [id] => 3986128 [patent_doc_number] => 05919261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Methods and apparatus for controlling operation of a link layer controller based upon a state of connection between multiple electronic apparatus' [patent_app_type] => 1 [patent_app_number] => 8/910854 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/919/05919261.pdf [firstpage_image] =>[orig_patent_app_number] => 910854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910854
Methods and apparatus for controlling operation of a link layer controller based upon a state of connection between multiple electronic apparatus Aug 12, 1997 Issued
Array ( [id] => 3969942 [patent_doc_number] => 05958033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies' [patent_app_type] => 1 [patent_app_number] => 8/910278 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4069 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/958/05958033.pdf [firstpage_image] =>[orig_patent_app_number] => 910278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910278
On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies Aug 12, 1997 Issued
Array ( [id] => 4008564 [patent_doc_number] => 05920727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Timer-controlled computer system shutdown and startup' [patent_app_type] => 1 [patent_app_number] => 8/908534 [patent_app_country] => US [patent_app_date] => 1997-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2555 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920727.pdf [firstpage_image] =>[orig_patent_app_number] => 908534 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908534
Timer-controlled computer system shutdown and startup Aug 6, 1997 Issued
Array ( [id] => 4057623 [patent_doc_number] => 05913043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'State machine based bus bridge performance and resource usage monitoring in a bus bridge verification system' [patent_app_type] => 1 [patent_app_number] => 8/904501 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9380 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913043.pdf [firstpage_image] =>[orig_patent_app_number] => 904501 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904501
State machine based bus bridge performance and resource usage monitoring in a bus bridge verification system Jul 31, 1997 Issued
Array ( [id] => 4026045 [patent_doc_number] => 05941971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Bus bridge transaction checker for correct resolution of combined data cycles' [patent_app_type] => 1 [patent_app_number] => 8/904195 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9381 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941971.pdf [firstpage_image] =>[orig_patent_app_number] => 904195 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904195
Bus bridge transaction checker for correct resolution of combined data cycles Jul 30, 1997 Issued
Array ( [id] => 3955072 [patent_doc_number] => 05930482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Transaction checking system for verifying bus bridges in multi-master bus systems' [patent_app_type] => 1 [patent_app_number] => 8/904504 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930482.pdf [firstpage_image] =>[orig_patent_app_number] => 904504 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904504
Transaction checking system for verifying bus bridges in multi-master bus systems Jul 30, 1997 Issued
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