Gopal C. Ray

Array ( [id] => 3970318 [patent_doc_number] => 05991840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Computer expansion unit with circuitry for reliable communication on auxiliary bus' [patent_app_type] => 1 [patent_app_number] => 8/902634 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991840.pdf [firstpage_image] =>[orig_patent_app_number] => 902634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3962069 [patent_doc_number] => 05974541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'GPIB system and method which provides asynchronous event notification' [patent_app_type] => 1 [patent_app_number] => 8/898050 [patent_app_country] => US [patent_app_date] => 1997-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974541.pdf [firstpage_image] =>[orig_patent_app_number] => 898050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3973117 [patent_doc_number] => 05978869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Enhanced dual speed bus computer system' [patent_app_type] => 1 [patent_app_number] => 8/897573 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2557 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978869.pdf [firstpage_image] =>[orig_patent_app_number] => 897573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3924142 [patent_doc_number] => 05938770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Display apparatus for computer system' [patent_app_type] => 1 [patent_app_number] => 8/897760 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 6176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938770.pdf [firstpage_image] =>[orig_patent_app_number] => 897760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4040356 [patent_doc_number] => 05884052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Smart retry mechanism to program the retry latency of a PCI initiator agent' [patent_app_type] => 1 [patent_app_number] => 8/897216 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5149 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884052.pdf [firstpage_image] =>[orig_patent_app_number] => 897216 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3987720 [patent_doc_number] => 05922068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Information processing system and information processing method for executing instructions in parallel' [patent_app_type] => 1 [patent_app_number] => 8/888645 [patent_app_country] => US [patent_app_date] => 1997-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13159 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/922/05922068.pdf [firstpage_image] =>[orig_patent_app_number] => 888645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 984585 [patent_doc_number] => 06928500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-09 [patent_title] => 'High speed bus system that incorporates uni-directional point-to-point buses' [patent_app_type] => utility [patent_app_number] => 08/883118 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8443 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928500.pdf [firstpage_image] =>[orig_patent_app_number] => 08883118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3807373 [patent_doc_number] => 05842027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Method and apparatus for supplying power to devices coupled to a bus' [patent_app_type] => 1 [patent_app_number] => 8/878859 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7455 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/842/05842027.pdf [firstpage_image] =>[orig_patent_app_number] => 878859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057232 [patent_doc_number] => 05875308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Peripheral component interconnect (PCI) architecture having hot-plugging capability for a data-processing system' [patent_app_type] => 1 [patent_app_number] => 8/878025 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2963 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875308.pdf [firstpage_image] =>[orig_patent_app_number] => 878025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3849391 [patent_doc_number] => 05761447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Adaptor connection apparatus for simultaneously connecting a plurality of adaptors to diverse bus architectures' [patent_app_type] => 1 [patent_app_number] => 8/876359 [patent_app_country] => US [patent_app_date] => 1997-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3763 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761447.pdf [firstpage_image] =>[orig_patent_app_number] => 876359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4040343 [patent_doc_number] => 05884051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities' [patent_app_type] => 1 [patent_app_number] => 8/874639 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8036 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884051.pdf [firstpage_image] =>[orig_patent_app_number] => 874639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3924184 [patent_doc_number] => 05938772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Responsive backlit hardwire button array providing illumination and user feedback in a computer' [patent_app_type] => 1 [patent_app_number] => 8/872715 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7582 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938772.pdf [firstpage_image] =>[orig_patent_app_number] => 872715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3997962 [patent_doc_number] => 05949982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Data processing system and method for implementing a switch protocol in a communication system' [patent_app_type] => 1 [patent_app_number] => 8/872476 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6298 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949982.pdf [firstpage_image] =>[orig_patent_app_number] => 872476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3849415 [patent_doc_number] => 05761449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Bus system providing dynamic control of pipeline depth for a multi-agent computer' [patent_app_type] => 1 [patent_app_number] => 8/871593 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5209 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761449.pdf [firstpage_image] =>[orig_patent_app_number] => 871593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3850281 [patent_doc_number] => 05815734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'System and method for reconfiguring configuration registers of a PCI bus device in response to a change in clock signal frequency' [patent_app_type] => 1 [patent_app_number] => 8/868797 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3875 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815734.pdf [firstpage_image] =>[orig_patent_app_number] => 868797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3797146 [patent_doc_number] => 05758169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Protocol for interrupt bus arbitration in a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 8/868370 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 9737 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/758/05758169.pdf [firstpage_image] =>[orig_patent_app_number] => 868370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057773 [patent_doc_number] => 05875342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'User programmable interrupt mask with timeout' [patent_app_type] => 1 [patent_app_number] => 8/868400 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875342.pdf [firstpage_image] =>[orig_patent_app_number] => 868400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4008579 [patent_doc_number] => 05892957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system' [patent_app_type] => 1 [patent_app_number] => 8/868171 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 14325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892957.pdf [firstpage_image] =>[orig_patent_app_number] => 868171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3803241 [patent_doc_number] => 05822594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Network hub interconnection circuitry having power reset feature' [patent_app_type] => 1 [patent_app_number] => 8/867741 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2211 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822594.pdf [firstpage_image] =>[orig_patent_app_number] => 867741 [rel_patent_id] =>[rel_patent_doc_number] =>)