Gopal C. Ray

Array ( [id] => 3952271 [patent_doc_number] => 05872981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Method for managing termination of a lock-holding process using a waiting lock' [patent_app_type] => 1 [patent_app_number] => 8/865885 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872981.pdf [firstpage_image] =>[orig_patent_app_number] => 865885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3967000 [patent_doc_number] => 05983303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Bus arrangements for interconnection of discrete and/or integrated modules in a digital system and associated method' [patent_app_type] => 1 [patent_app_number] => 8/863875 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 36724 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983303.pdf [firstpage_image] =>[orig_patent_app_number] => 863875 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3910030 [patent_doc_number] => 05835736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Serial data transmission unit' [patent_app_type] => 1 [patent_app_number] => 8/861625 [patent_app_country] => US [patent_app_date] => 1997-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1571 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835736.pdf [firstpage_image] =>[orig_patent_app_number] => 861625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3955013 [patent_doc_number] => 05900026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method and apparatus for setting a computer coupled to a network into a power saving mode' [patent_app_type] => 1 [patent_app_number] => 8/861324 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5162 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900026.pdf [firstpage_image] =>[orig_patent_app_number] => 861324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3923884 [patent_doc_number] => 05938752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'System and method for encapsulating legacy data transport protocols for IEEE 1394 serial bus' [patent_app_type] => 1 [patent_app_number] => 8/859613 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3366 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/938/05938752.pdf [firstpage_image] =>[orig_patent_app_number] => 859613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4215439 [patent_doc_number] => 06014722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Data communication system for controlling prioritization and transfer of data and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/858439 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2184 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014722.pdf [firstpage_image] =>[orig_patent_app_number] => 858439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3989823 [patent_doc_number] => 05905899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Power control device in printer and method for controlling the same' [patent_app_type] => 1 [patent_app_number] => 8/854721 [patent_app_country] => US [patent_app_date] => 1997-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2836 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905899.pdf [firstpage_image] =>[orig_patent_app_number] => 854721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3903597 [patent_doc_number] => 05724606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Extended peripheral bus with bidirectional transmission' [patent_app_type] => 1 [patent_app_number] => 8/854590 [patent_app_country] => US [patent_app_date] => 1997-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3438 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724606.pdf [firstpage_image] =>[orig_patent_app_number] => 854590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3808666 [patent_doc_number] => 05727219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Virtual input/output processor utilizing an interrupt handler' [patent_app_type] => 1 [patent_app_number] => 8/854113 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727219.pdf [firstpage_image] =>[orig_patent_app_number] => 854113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3989467 [patent_doc_number] => 05905877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'PCI host bridge multi-priority fairness arbiter' [patent_app_type] => 1 [patent_app_number] => 8/853776 [patent_app_country] => US [patent_app_date] => 1997-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6770 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905877.pdf [firstpage_image] =>[orig_patent_app_number] => 853776 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4025977 [patent_doc_number] => 05941966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method and apparatus using a plural level processor for controlling a data bus' [patent_app_type] => 1 [patent_app_number] => 8/842468 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2950 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941966.pdf [firstpage_image] =>[orig_patent_app_number] => 842468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057246 [patent_doc_number] => 05875309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Arbitration system using linked table' [patent_app_type] => 1 [patent_app_number] => 8/843957 [patent_app_country] => US [patent_app_date] => 1997-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 9293 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875309.pdf [firstpage_image] =>[orig_patent_app_number] => 843957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4040873 [patent_doc_number] => 05884086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'System and method for voltage switching to supply various voltages and power levels to a peripheral device' [patent_app_type] => 1 [patent_app_number] => 8/842695 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4537 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884086.pdf [firstpage_image] =>[orig_patent_app_number] => 842695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3973145 [patent_doc_number] => 05978871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method of layering cache and architectural specific functions for operation splitting' [patent_app_type] => 1 [patent_app_number] => 8/834114 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978871.pdf [firstpage_image] =>[orig_patent_app_number] => 834114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3973214 [patent_doc_number] => 05978876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'System and method for controlling communications between subsystems' [patent_app_type] => 1 [patent_app_number] => 8/834242 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978876.pdf [firstpage_image] =>[orig_patent_app_number] => 834242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3915882 [patent_doc_number] => 05951659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Communications-oriented computer system backplane including a PCI input/output bus for transmission of address, data, and control information, and a time-domain multiplexed signal bus (TDMSB) for transmission of high-speed digitized signal information' [patent_app_type] => 1 [patent_app_number] => 8/834568 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1113 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951659.pdf [firstpage_image] =>[orig_patent_app_number] => 834568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4056907 [patent_doc_number] => 05909559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Bus bridge device including data bus of first width for a first processor, memory controller, arbiter circuit and second processor having a different second data width' [patent_app_type] => 1 [patent_app_number] => 8/832892 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 104 [patent_figures_cnt] => 159 [patent_no_of_words] => 76844 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909559.pdf [firstpage_image] =>[orig_patent_app_number] => 832892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3983921 [patent_doc_number] => 05887147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Display apparatus' [patent_app_type] => 1 [patent_app_number] => 8/833346 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5759 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887147.pdf [firstpage_image] =>[orig_patent_app_number] => 833346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4036709 [patent_doc_number] => 05968152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Method and apparatus for extending key space in a plug and play ROM' [patent_app_type] => 1 [patent_app_number] => 8/833337 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4478 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968152.pdf [firstpage_image] =>[orig_patent_app_number] => 833337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3945032 [patent_doc_number] => 05935229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Bidirectional sequential interaction designation scheme for a chained and bussed array of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/829709 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8201 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935229.pdf [firstpage_image] =>[orig_patent_app_number] => 829709 [rel_patent_id] =>[rel_patent_doc_number] =>)