Gopal C. Ray

Array ( [id] => 2645884 [patent_doc_number] => 04939353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-03 [patent_title] => 'Processing system for enabling data communication with a self-diagnose device' [patent_app_type] => 1 [patent_app_number] => 7/143654 [patent_app_country] => US [patent_app_date] => 1988-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4359 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/939/04939353.pdf [firstpage_image] =>[orig_patent_app_number] => 143654 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2610913 [patent_doc_number] => 04931924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-05 [patent_title] => 'Data transfer speed control apparatus capable of varying speed of data transfer between devices having different transfer speeds' [patent_app_type] => 1 [patent_app_number] => 7/133805 [patent_app_country] => US [patent_app_date] => 1987-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1993 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/931/04931924.pdf [firstpage_image] =>[orig_patent_app_number] => 133805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2601304 [patent_doc_number] => 04918587 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-17 [patent_title] => 'Prefetch circuit for a computer memory subject to consecutive addressing' [patent_app_type] => 1 [patent_app_number] => 7/131602 [patent_app_country] => US [patent_app_date] => 1987-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3016 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/918/04918587.pdf [firstpage_image] =>[orig_patent_app_number] => 131602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2633533 [patent_doc_number] => 04920486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-24 [patent_title] => 'Distributed arbitration apparatus and method for shared bus' [patent_app_type] => 1 [patent_app_number] => 7/123382 [patent_app_country] => US [patent_app_date] => 1987-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4502 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/920/04920486.pdf [firstpage_image] =>[orig_patent_app_number] => 123382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2673264 [patent_doc_number] => 04947411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-07 [patent_title] => 'Programmable clock frequency divider' [patent_app_type] => 1 [patent_app_number] => 7/123553 [patent_app_country] => US [patent_app_date] => 1987-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5669 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/947/04947411.pdf [firstpage_image] =>[orig_patent_app_number] => 123553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2565774 [patent_doc_number] => 04942525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-17 [patent_title] => 'Data processor for concurrent executing of instructions by plural execution units' [patent_app_type] => 1 [patent_app_number] => 7/123139 [patent_app_country] => US [patent_app_date] => 1987-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 13151 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/942/04942525.pdf [firstpage_image] =>[orig_patent_app_number] => 123139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2607887 [patent_doc_number] => 04922438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-01 [patent_title] => 'Method and apparatus for reading packet-oriented data signals into and out of a buffer' [patent_app_type] => 1 [patent_app_number] => 7/122834 [patent_app_country] => US [patent_app_date] => 1987-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3902 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/922/04922438.pdf [firstpage_image] =>[orig_patent_app_number] => 122834 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2565693 [patent_doc_number] => 04942521 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-17 [patent_title] => 'Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable' [patent_app_type] => 1 [patent_app_number] => 7/119919 [patent_app_country] => US [patent_app_date] => 1987-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3698 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/942/04942521.pdf [firstpage_image] =>[orig_patent_app_number] => 119919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2653550 [patent_doc_number] => 04939755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-03 [patent_title] => 'Timer/counter using a register block' [patent_app_type] => 1 [patent_app_number] => 7/119515 [patent_app_country] => US [patent_app_date] => 1987-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4821 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/939/04939755.pdf [firstpage_image] =>[orig_patent_app_number] => 119515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2617859 [patent_doc_number] => 04903194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-20 [patent_title] => 'Storage addressing error detection circuitry' [patent_app_type] => 1 [patent_app_number] => 7/119756 [patent_app_country] => US [patent_app_date] => 1987-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3395 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/903/04903194.pdf [firstpage_image] =>[orig_patent_app_number] => 119756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2664753 [patent_doc_number] => 04930068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-29 [patent_title] => 'Data processor having different interrupt processing modes' [patent_app_type] => 1 [patent_app_number] => 7/118671 [patent_app_country] => US [patent_app_date] => 1987-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8964 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/930/04930068.pdf [firstpage_image] =>[orig_patent_app_number] => 118671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2611872 [patent_doc_number] => 04949243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-14 [patent_title] => 'Data processing system intended for the execution of programs in the form of search trees, so-called or parallel execution' [patent_app_type] => 1 [patent_app_number] => 7/124116 [patent_app_country] => US [patent_app_date] => 1987-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5904 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/949/04949243.pdf [firstpage_image] =>[orig_patent_app_number] => 124116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2642796 [patent_doc_number] => 04953078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-28 [patent_title] => 'Apparatus and method for multi-threaded program execution in a microcoded data processing system' [patent_app_type] => 1 [patent_app_number] => 7/114644 [patent_app_country] => US [patent_app_date] => 1987-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2938 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/953/04953078.pdf [firstpage_image] =>[orig_patent_app_number] => 114644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2647151 [patent_doc_number] => 04914619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-03 [patent_title] => 'Apparatus and method for interconnecting an application of a transparent services access facility to remote source' [patent_app_type] => 1 [patent_app_number] => 7/109366 [patent_app_country] => US [patent_app_date] => 1987-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3088 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/914/04914619.pdf [firstpage_image] =>[orig_patent_app_number] => 109366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2623575 [patent_doc_number] => 04943915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-24 [patent_title] => 'Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit' [patent_app_type] => 1 [patent_app_number] => 7/101984 [patent_app_country] => US [patent_app_date] => 1987-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3482 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/943/04943915.pdf [firstpage_image] =>[orig_patent_app_number] => 101984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2607436 [patent_doc_number] => 04965801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-23 [patent_title] => 'Architectural arrangement for a SCSI disk controller integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/101452 [patent_app_country] => US [patent_app_date] => 1987-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8275 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/965/04965801.pdf [firstpage_image] =>[orig_patent_app_number] => 101452 [rel_patent_id] =>[rel_patent_doc_number] =>)