Search

Grant S. Withers

Examiner (ID: 18926, Phone: (571)270-1570 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2895, 2817, 2812, 2891
Total Applications
1000
Issued Applications
834
Pending Applications
38
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8499648 [patent_doc_number] => 20120299056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/479360 [patent_app_country] => US [patent_app_date] => 2012-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 61 [patent_no_of_words] => 17300 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479360 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/479360
Method of manufacturing semiconductor device and semiconductor device May 23, 2012 Issued
Array ( [id] => 9311699 [patent_doc_number] => 08652917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Superior stability of characteristics of transistors having an early formed high-K metal gate' [patent_app_type] => utility [patent_app_number] => 13/478519 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 9349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13478519 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/478519
Superior stability of characteristics of transistors having an early formed high-K metal gate May 22, 2012 Issued
Array ( [id] => 8875749 [patent_doc_number] => 08470714 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-25 [patent_title] => 'Method of forming fin structures in integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/477079 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2535 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477079 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477079
Method of forming fin structures in integrated circuits May 21, 2012 Issued
Array ( [id] => 8495992 [patent_doc_number] => 20120295400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/475753 [patent_app_country] => US [patent_app_date] => 2012-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8257 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13475753 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/475753
METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE May 17, 2012 Abandoned
Array ( [id] => 10863862 [patent_doc_number] => 08889560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Methods of forming fine patterns for semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/474764 [patent_app_country] => US [patent_app_date] => 2012-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7515 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13474764 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/474764
Methods of forming fine patterns for semiconductor device May 17, 2012 Issued
Array ( [id] => 8496026 [patent_doc_number] => 20120295434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'SOLDER COLLAPSE FREE BUMPING PROCESS OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/473728 [patent_app_country] => US [patent_app_date] => 2012-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3693 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13473728 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/473728
Solder collapse free bumping process of semiconductor device May 16, 2012 Issued
Array ( [id] => 9161514 [patent_doc_number] => 20130309791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR' [patent_app_type] => utility [patent_app_number] => 13/472584 [patent_app_country] => US [patent_app_date] => 2012-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5839 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13472584 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/472584
Semiconductor active matrix on buried insulator May 15, 2012 Issued
Array ( [id] => 8995579 [patent_doc_number] => 08519466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Tantalum silicon oxynitride high-K dielectrics and metal gates' [patent_app_type] => utility [patent_app_number] => 13/458196 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 17450 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458196 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458196
Tantalum silicon oxynitride high-K dielectrics and metal gates Apr 26, 2012 Issued
Array ( [id] => 9534384 [patent_doc_number] => 20140159031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'ORGANIC LIGHT-EMITTING ELEMENT' [patent_app_type] => utility [patent_app_number] => 14/235895 [patent_app_country] => US [patent_app_date] => 2012-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8769 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14235895 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/235895
Organic light-emitting element with regulation insulating layer and two-component electron transport layer and method of making Apr 10, 2012 Issued
Array ( [id] => 10897911 [patent_doc_number] => 08921125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Method of making ferroelectric memory device with barrier layer and novolac resin passivation layer' [patent_app_type] => utility [patent_app_number] => 13/442217 [patent_app_country] => US [patent_app_date] => 2012-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 8886 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442217 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/442217
Method of making ferroelectric memory device with barrier layer and novolac resin passivation layer Apr 8, 2012 Issued
Array ( [id] => 8875658 [patent_doc_number] => 08470622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-25 [patent_title] => 'Method for manufacturing array substrate of transmissive liquid crystal display' [patent_app_type] => utility [patent_app_number] => 13/509994 [patent_app_country] => US [patent_app_date] => 2012-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2468 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13509994 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/509994
Method for manufacturing array substrate of transmissive liquid crystal display Mar 10, 2012 Issued
Array ( [id] => 9389165 [patent_doc_number] => 08685761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Method for making a redistributed electronic device using a transferrable redistribution layer' [patent_app_type] => utility [patent_app_number] => 13/364836 [patent_app_country] => US [patent_app_date] => 2012-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3104 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364836 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364836
Method for making a redistributed electronic device using a transferrable redistribution layer Feb 1, 2012 Issued
Array ( [id] => 8963588 [patent_doc_number] => 20130203190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'METHOD FOR MAKING A REDISTRIBUTED WAFER USING TRANSFERRABLE REDISTRIBUTION LAYERS' [patent_app_type] => utility [patent_app_number] => 13/364858 [patent_app_country] => US [patent_app_date] => 2012-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3182 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364858 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364858
Method for making a redistributed wafer using transferrable redistribution layers Feb 1, 2012 Issued
Array ( [id] => 9232682 [patent_doc_number] => 08597985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-03 [patent_title] => 'MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads' [patent_app_type] => utility [patent_app_number] => 13/364166 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2949 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364166 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364166
MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads Jan 31, 2012 Issued
Array ( [id] => 8950700 [patent_doc_number] => 20130196481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'METHOD OF PATTERNING FOR A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/364119 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364119 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364119
Method of patterning for a semiconductor device Jan 31, 2012 Issued
Array ( [id] => 9440836 [patent_doc_number] => 08709946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Method for forming contact hole' [patent_app_type] => utility [patent_app_number] => 13/364252 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3852 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364252 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364252
Method for forming contact hole Jan 31, 2012 Issued
Array ( [id] => 8947784 [patent_doc_number] => 20130193564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD AND TOOL FOR FORMING THE SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/364069 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364069 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364069
Semiconductor structure and method and tool for forming the semiconductor structure Jan 31, 2012 Issued
Array ( [id] => 8287381 [patent_doc_number] => 20120175716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'STORAGE ELEMENT AND STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/332664 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10520 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332664
Storage element and storage device Dec 20, 2011 Issued
Array ( [id] => 8888626 [patent_doc_number] => 20130161810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/332658 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2785 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332658 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332658
Semiconductor package Dec 20, 2011 Issued
Array ( [id] => 8192876 [patent_doc_number] => 20120119293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'HIGH PERFORMANCE LDMOS DEVICE HAVING ENHANCED DIELECTRIC STRAIN LAYER' [patent_app_type] => utility [patent_app_number] => 13/333118 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2076 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119293.pdf [firstpage_image] =>[orig_patent_app_number] => 13333118 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333118
High performance LDMOS device having enhanced dielectric strain layer Dec 20, 2011 Issued
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