Search

Grant S. Withers

Examiner (ID: 18926, Phone: (571)270-1570 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2895, 2817, 2812, 2891
Total Applications
1000
Issued Applications
834
Pending Applications
38
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7564906 [patent_doc_number] => 20110284969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'SEMICONDUCTOR DEVICE, METHOD OF FORMING SEMICONDUCTOR DEVICE, AND DATA PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/105437 [patent_app_country] => US [patent_app_date] => 2011-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 26320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20110284969.pdf [firstpage_image] =>[orig_patent_app_number] => 13105437 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/105437
Semiconductor device, method of forming semiconductor device, and data processing system May 10, 2011 Issued
Array ( [id] => 6161885 [patent_doc_number] => 20110159655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING' [patent_app_type] => utility [patent_app_number] => 13/045679 [patent_app_country] => US [patent_app_date] => 2011-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3234 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20110159655.pdf [firstpage_image] =>[orig_patent_app_number] => 13045679 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/045679
Stress enhanced transistor devices and methods of making Mar 10, 2011 Issued
Array ( [id] => 8233263 [patent_doc_number] => 08198708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'System and method for improving CMOS compatible non volatile memory retention reliability' [patent_app_type] => utility [patent_app_number] => 13/040844 [patent_app_country] => US [patent_app_date] => 2011-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/198/08198708.pdf [firstpage_image] =>[orig_patent_app_number] => 13040844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/040844
System and method for improving CMOS compatible non volatile memory retention reliability Mar 3, 2011 Issued
Array ( [id] => 8675396 [patent_doc_number] => 08383509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy and semiconductor device of this kind' [patent_app_type] => utility [patent_app_number] => 13/036522 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 9335 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13036522 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/036522
Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy and semiconductor device of this kind Feb 27, 2011 Issued
Array ( [id] => 5971031 [patent_doc_number] => 20110151595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'Fabrication method for semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/929914 [patent_app_country] => US [patent_app_date] => 2011-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6814 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20110151595.pdf [firstpage_image] =>[orig_patent_app_number] => 12929914 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929914
Fabrication method for semiconductor device Feb 23, 2011 Issued
Array ( [id] => 8153115 [patent_doc_number] => 08169048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Isolation structure in a memory device' [patent_app_type] => utility [patent_app_number] => 13/023992 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9625 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/169/08169048.pdf [firstpage_image] =>[orig_patent_app_number] => 13023992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/023992
Isolation structure in a memory device Feb 8, 2011 Issued
Array ( [id] => 5996847 [patent_doc_number] => 20110115045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'SUBSTRATE FOR MANUFACTURING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/008241 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 20865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20110115045.pdf [firstpage_image] =>[orig_patent_app_number] => 13008241 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008241
Substrate for manufacturing semiconductor device and manufacturing method thereof Jan 17, 2011 Issued
Array ( [id] => 6120947 [patent_doc_number] => 20110084407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'SYSTEM AND METHOD FOR PREVENTING METAL CORROSION ON BOND PADS' [patent_app_type] => utility [patent_app_number] => 12/971513 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2667 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084407.pdf [firstpage_image] =>[orig_patent_app_number] => 12971513 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971513
SYSTEM AND METHOD FOR PREVENTING METAL CORROSION ON BOND PADS Dec 16, 2010 Abandoned
Array ( [id] => 6075342 [patent_doc_number] => 20110140244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-16 [patent_title] => 'METHOD FOR ROUTING A CHAMFERED SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/965135 [patent_app_country] => US [patent_app_date] => 2010-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20110140244.pdf [firstpage_image] =>[orig_patent_app_number] => 12965135 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/965135
Method for routing a chamfered substrate Dec 9, 2010 Issued
Array ( [id] => 8469666 [patent_doc_number] => 08298844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Method of forming organic thin film pattern and method of manufacturing organic light-emitting display device by using the method of forming organic thin film pattern' [patent_app_type] => utility [patent_app_number] => 12/963928 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 6119 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963928 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963928
Method of forming organic thin film pattern and method of manufacturing organic light-emitting display device by using the method of forming organic thin film pattern Dec 8, 2010 Issued
Array ( [id] => 5936947 [patent_doc_number] => 20110212591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'METHOD FOR FABRICATING TRANSISTOR OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/964562 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2979 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20110212591.pdf [firstpage_image] =>[orig_patent_app_number] => 12964562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/964562
METHOD FOR FABRICATING TRANSISTOR OF SEMICONDUCTOR DEVICE Dec 8, 2010 Abandoned
Array ( [id] => 7570982 [patent_doc_number] => 20110266638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Semiconductor Device Comprising Contact Elements and Metal Silicide Regions Formed in a Common Process Sequence' [patent_app_type] => utility [patent_app_number] => 12/964020 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266638.pdf [firstpage_image] =>[orig_patent_app_number] => 12964020 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/964020
Semiconductor Device Comprising Contact Elements and Metal Silicide Regions Formed in a Common Process Sequence Dec 8, 2010 Abandoned
Array ( [id] => 8469695 [patent_doc_number] => 08298872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Manufacturing method for semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/964204 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8770 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12964204 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/964204
Manufacturing method for semiconductor device Dec 8, 2010 Issued
Array ( [id] => 7573622 [patent_doc_number] => 20110269278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'Stress Memorization with Reduced Fringing Capacitance Based on Silicon Nitride in MOS Semiconductor Devices' [patent_app_type] => utility [patent_app_number] => 12/963753 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20110269278.pdf [firstpage_image] =>[orig_patent_app_number] => 12963753 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963753
Stress memorization with reduced fringing capacitance based on silicon nitride in MOS semiconductor devices Dec 8, 2010 Issued
Array ( [id] => 8933190 [patent_doc_number] => 08492892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Solder bump connections' [patent_app_type] => utility [patent_app_number] => 12/963139 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5285 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963139
Solder bump connections Dec 7, 2010 Issued
Array ( [id] => 8701494 [patent_doc_number] => 08394716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Methods of manufacturing three-dimensional semiconductor devices and related devices' [patent_app_type] => utility [patent_app_number] => 12/963241 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 36 [patent_no_of_words] => 14202 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12963241 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/963241
Methods of manufacturing three-dimensional semiconductor devices and related devices Dec 7, 2010 Issued
Array ( [id] => 6202470 [patent_doc_number] => 20110065256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'SYSTEM AND METHOD FOR INCREASING BREAKDOWN VOLTAGE OF LOCOS ISOLATED DEVICES' [patent_app_type] => utility [patent_app_number] => 12/955194 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2843 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20110065256.pdf [firstpage_image] =>[orig_patent_app_number] => 12955194 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/955194
SYSTEM AND METHOD FOR INCREASING BREAKDOWN VOLTAGE OF LOCOS ISOLATED DEVICES Nov 28, 2010 Abandoned
Array ( [id] => 6137553 [patent_doc_number] => 20110127654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'Semiconductor Package and Manufacturing Methods Thereof' [patent_app_type] => utility [patent_app_number] => 12/955782 [patent_app_country] => US [patent_app_date] => 2010-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20110127654.pdf [firstpage_image] =>[orig_patent_app_number] => 12955782 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/955782
Semiconductor Package and Manufacturing Methods Thereof Nov 28, 2010 Abandoned
Array ( [id] => 6199720 [patent_doc_number] => 20110062506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Metal Oxide Semiconductor Field Effect Transistor Integrating a Capacitor' [patent_app_type] => utility [patent_app_number] => 12/947107 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8005 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20110062506.pdf [firstpage_image] =>[orig_patent_app_number] => 12947107 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/947107
Metal oxide semiconductor field effect transistor integrating a capacitor Nov 15, 2010 Issued
Array ( [id] => 8192848 [patent_doc_number] => 20120119273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP' [patent_app_type] => utility [patent_app_number] => 12/946915 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119273.pdf [firstpage_image] =>[orig_patent_app_number] => 12946915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/946915
Hydrogen barrier liner for ferro-electric random access memory (FRAM) chip Nov 15, 2010 Issued
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