Search

Grant S. Withers

Examiner (ID: 18926, Phone: (571)270-1570 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2895, 2817, 2812, 2891
Total Applications
1000
Issued Applications
834
Pending Applications
38
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4455781 [patent_doc_number] => 07892919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Method of forming isolation layer in semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/163328 [patent_app_country] => US [patent_app_date] => 2008-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2923 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/892/07892919.pdf [firstpage_image] =>[orig_patent_app_number] => 12163328 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/163328
Method of forming isolation layer in semiconductor device Jun 26, 2008 Issued
Array ( [id] => 6624749 [patent_doc_number] => 20100311248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'STRUCTURED LAYER DEPOSITION ON PROCESSED WAFERS USED IN MICROSYSTEM TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 12/664272 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2431 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0311/20100311248.pdf [firstpage_image] =>[orig_patent_app_number] => 12664272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/664272
STRUCTURED LAYER DEPOSITION ON PROCESSED WAFERS USED IN MICROSYSTEM TECHNOLOGY Jun 15, 2008 Abandoned
Array ( [id] => 4507098 [patent_doc_number] => 07915149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Gallium nitride substrate and gallium nitride layer formation method' [patent_app_type] => utility [patent_app_number] => 12/136275 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9531 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915149.pdf [firstpage_image] =>[orig_patent_app_number] => 12136275 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136275
Gallium nitride substrate and gallium nitride layer formation method Jun 9, 2008 Issued
Array ( [id] => 4634965 [patent_doc_number] => 08013419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Structure and method to form dual silicide e-fuse' [patent_app_type] => utility [patent_app_number] => 12/136246 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2650 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/013/08013419.pdf [firstpage_image] =>[orig_patent_app_number] => 12136246 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136246
Structure and method to form dual silicide e-fuse Jun 9, 2008 Issued
Array ( [id] => 5567444 [patent_doc_number] => 20090250822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'MULTI-CHIP STACK PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/136055 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4876 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20090250822.pdf [firstpage_image] =>[orig_patent_app_number] => 12136055 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136055
Multi-chip stack package Jun 9, 2008 Issued
Array ( [id] => 5364789 [patent_doc_number] => 20090302348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING' [patent_app_type] => utility [patent_app_number] => 12/136195 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302348.pdf [firstpage_image] =>[orig_patent_app_number] => 12136195 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136195
STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING Jun 9, 2008 Abandoned
Array ( [id] => 4644302 [patent_doc_number] => 08021907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Method and apparatus for thermally enhanced semiconductor package' [patent_app_type] => utility [patent_app_number] => 12/135830 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 50 [patent_no_of_words] => 9946 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/021/08021907.pdf [firstpage_image] =>[orig_patent_app_number] => 12135830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135830
Method and apparatus for thermally enhanced semiconductor package Jun 8, 2008 Issued
Array ( [id] => 8146612 [patent_doc_number] => 08163621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'High performance LDMOS device having enhanced dielectric strain layer' [patent_app_type] => utility [patent_app_number] => 12/134860 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2076 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/163/08163621.pdf [firstpage_image] =>[orig_patent_app_number] => 12134860 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/134860
High performance LDMOS device having enhanced dielectric strain layer Jun 5, 2008 Issued
Array ( [id] => 4946973 [patent_doc_number] => 20080303099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'Semiconductor Device and Fabrication Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/134516 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10206 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20080303099.pdf [firstpage_image] =>[orig_patent_app_number] => 12134516 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/134516
Semiconductor device and fabrication method thereof Jun 5, 2008 Issued
Array ( [id] => 4619096 [patent_doc_number] => 07998814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Semiconductor memory device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 12/133775 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1745 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/998/07998814.pdf [firstpage_image] =>[orig_patent_app_number] => 12133775 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133775
Semiconductor memory device and method of fabricating the same Jun 4, 2008 Issued
Array ( [id] => 4496035 [patent_doc_number] => 07956415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'SOI transistor having a carrier recombination structure in a body' [patent_app_type] => utility [patent_app_number] => 12/133686 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 8032 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/956/07956415.pdf [firstpage_image] =>[orig_patent_app_number] => 12133686 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133686
SOI transistor having a carrier recombination structure in a body Jun 4, 2008 Issued
Array ( [id] => 4539300 [patent_doc_number] => 07875532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Substrate for manufacturing semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/155340 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 55 [patent_no_of_words] => 20865 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/875/07875532.pdf [firstpage_image] =>[orig_patent_app_number] => 12155340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155340
Substrate for manufacturing semiconductor device and manufacturing method thereof Jun 2, 2008 Issued
Array ( [id] => 5346083 [patent_doc_number] => 20090001444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/132450 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2802 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20090001444.pdf [firstpage_image] =>[orig_patent_app_number] => 12132450 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/132450
Semiconductor device and manufacturing method thereof Jun 2, 2008 Issued
Array ( [id] => 7713462 [patent_doc_number] => 08093704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Package on package using a bump-less build up layer (BBUL) package' [patent_app_type] => utility [patent_app_number] => 12/132085 [patent_app_country] => US [patent_app_date] => 2008-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2331 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093704.pdf [firstpage_image] =>[orig_patent_app_number] => 12132085 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/132085
Package on package using a bump-less build up layer (BBUL) package Jun 2, 2008 Issued
Array ( [id] => 4708081 [patent_doc_number] => 20080296607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'ENVIRONMENTALLY ROBUST LIGHTING DEVICES AND METHODS OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 12/129925 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4793 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296607.pdf [firstpage_image] =>[orig_patent_app_number] => 12129925 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129925
Environmentally robust lighting devices and methods of manufacturing same May 29, 2008 Issued
Array ( [id] => 4709466 [patent_doc_number] => 20080297992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'HOLLOW SEALING STRUCTURE AND MANUFACTURING METHOD FOR HOLLOW SEALING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/128956 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3809 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20080297992.pdf [firstpage_image] =>[orig_patent_app_number] => 12128956 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128956
HOLLOW SEALING STRUCTURE AND MANUFACTURING METHOD FOR HOLLOW SEALING STRUCTURE May 28, 2008 Abandoned
Array ( [id] => 4499814 [patent_doc_number] => 07919336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Fabrication method for semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/153499 [patent_app_country] => US [patent_app_date] => 2008-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 47 [patent_no_of_words] => 6781 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/919/07919336.pdf [firstpage_image] =>[orig_patent_app_number] => 12153499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153499
Fabrication method for semiconductor device May 19, 2008 Issued
Array ( [id] => 4492956 [patent_doc_number] => 07955964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Dishing-free gap-filling with multiple CMPs' [patent_app_type] => utility [patent_app_number] => 12/152380 [patent_app_country] => US [patent_app_date] => 2008-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 3324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/955/07955964.pdf [firstpage_image] =>[orig_patent_app_number] => 12152380 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/152380
Dishing-free gap-filling with multiple CMPs May 13, 2008 Issued
Array ( [id] => 8165733 [patent_doc_number] => 08174071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'High voltage LDMOS transistor' [patent_app_type] => utility [patent_app_number] => 12/114439 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174071.pdf [firstpage_image] =>[orig_patent_app_number] => 12114439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114439
High voltage LDMOS transistor May 1, 2008 Issued
Array ( [id] => 22200 [patent_doc_number] => 07799643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Method of fabricating semiconductor device having self-aligned contact plug' [patent_app_type] => utility [patent_app_number] => 12/112438 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7250 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/799/07799643.pdf [firstpage_image] =>[orig_patent_app_number] => 12112438 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112438
Method of fabricating semiconductor device having self-aligned contact plug Apr 29, 2008 Issued
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