Search

Grant S. Withers

Examiner (ID: 18926, Phone: (571)270-1570 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2895, 2817, 2812, 2891
Total Applications
1000
Issued Applications
834
Pending Applications
38
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4719489 [patent_doc_number] => 20080242012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'High quality silicon oxynitride transition layer for high-k/metal gate transistors' [patent_app_type] => utility [patent_app_number] => 11/729188 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3541 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20080242012.pdf [firstpage_image] =>[orig_patent_app_number] => 11729188 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/729188
High quality silicon oxynitride transition layer for high-k/metal gate transistors Mar 27, 2007 Abandoned
Array ( [id] => 4551363 [patent_doc_number] => 07820489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Method of manufacturing semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 11/727008 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4668 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/820/07820489.pdf [firstpage_image] =>[orig_patent_app_number] => 11727008 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727008
Method of manufacturing semiconductor apparatus Mar 22, 2007 Issued
Array ( [id] => 4977384 [patent_doc_number] => 20070218617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/724629 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5504 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20070218617.pdf [firstpage_image] =>[orig_patent_app_number] => 11724629 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724629
Method of manufacturing semiconductor device Mar 14, 2007 Abandoned
Array ( [id] => 4698416 [patent_doc_number] => 20080220600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Semiconductor constructions, methods of forming multiple lines, and methods of forming high density structures and low density structures with a single photomask' [patent_app_type] => utility [patent_app_number] => 11/714378 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5361 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20080220600.pdf [firstpage_image] =>[orig_patent_app_number] => 11714378 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/714378
Methods of forming multiple lines Mar 4, 2007 Issued
Array ( [id] => 33120 [patent_doc_number] => 07785908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method of making diode having reflective layer' [patent_app_type] => utility [patent_app_number] => 11/713045 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/785/07785908.pdf [firstpage_image] =>[orig_patent_app_number] => 11713045 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/713045
Method of making diode having reflective layer Mar 1, 2007 Issued
Array ( [id] => 5131232 [patent_doc_number] => 20070207629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'SURFACE PROTECTIVE FILM PEELING METHOD AND SURFACE PROTECTIVE FILM PEELING APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/680569 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5653 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20070207629.pdf [firstpage_image] =>[orig_patent_app_number] => 11680569 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680569
SURFACE PROTECTIVE FILM PEELING METHOD AND SURFACE PROTECTIVE FILM PEELING APPARATUS Feb 27, 2007 Abandoned
Array ( [id] => 4797542 [patent_doc_number] => 20080009128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Buried pattern substrate and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/708339 [patent_app_country] => US [patent_app_date] => 2007-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3442 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20080009128.pdf [firstpage_image] =>[orig_patent_app_number] => 11708339 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/708339
Buried pattern substrate and manufacturing method thereof Feb 20, 2007 Abandoned
Array ( [id] => 5989367 [patent_doc_number] => 20110012236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'EVALUATION OF AN UNDERCUT OF DEEP TRENCH STRUCTURES IN SOI WAFERS' [patent_app_type] => utility [patent_app_number] => 12/161669 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5626 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20110012236.pdf [firstpage_image] =>[orig_patent_app_number] => 12161669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/161669
EVALUATION OF AN UNDERCUT OF DEEP TRENCH STRUCTURES IN SOI WAFERS Jan 18, 2007 Abandoned
Array ( [id] => 4849471 [patent_doc_number] => 20080315213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Process for Producing an Electroluminescent P-N Junction Made of a Semiconductor Material by Molecular Bonding' [patent_app_type] => utility [patent_app_number] => 12/158050 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315213.pdf [firstpage_image] =>[orig_patent_app_number] => 12158050 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/158050
Process for Producing an Electroluminescent P-N Junction Made of a Semiconductor Material by Molecular Bonding Dec 25, 2006 Abandoned
Array ( [id] => 6512660 [patent_doc_number] => 20100261349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'UV TREATMENT FOR CARBON-CONTAINING LOW-K DIELECTRIC REPAIR IN SEMICONDUCTOR PROCESSING' [patent_app_type] => utility [patent_app_number] => 11/590661 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6294 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261349.pdf [firstpage_image] =>[orig_patent_app_number] => 11590661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590661
UV treatment for carbon-containing low-k dielectric repair in semiconductor processing Oct 29, 2006 Issued
Array ( [id] => 6501273 [patent_doc_number] => 20100012920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'III-Nitride Semiconductor Light Emitting Device' [patent_app_type] => utility [patent_app_number] => 12/084198 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4679 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20100012920.pdf [firstpage_image] =>[orig_patent_app_number] => 12084198 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/084198
III-nitride semiconductor light emitting device Oct 29, 2006 Issued
Array ( [id] => 5230927 [patent_doc_number] => 20070293035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Interlayer insulating layer and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/588981 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4793 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0293/20070293035.pdf [firstpage_image] =>[orig_patent_app_number] => 11588981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588981
Interlayer insulating layer and method of manufacturing the same Oct 26, 2006 Abandoned
Array ( [id] => 5002610 [patent_doc_number] => 20070200176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'FORMATION OF SILICIDED SURFACES FOR SILICON/CARBON SOURCE/DRAIN REGIONS' [patent_app_type] => utility [patent_app_number] => 11/550631 [patent_app_country] => US [patent_app_date] => 2006-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5763 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20070200176.pdf [firstpage_image] =>[orig_patent_app_number] => 11550631 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/550631
FORMATION OF SILICIDED SURFACES FOR SILICON/CARBON SOURCE/DRAIN REGIONS Oct 17, 2006 Abandoned
Array ( [id] => 236259 [patent_doc_number] => 07595240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Flash memory device with stacked dielectric structure including zirconium oxide and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/582705 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3728 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/595/07595240.pdf [firstpage_image] =>[orig_patent_app_number] => 11582705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/582705
Flash memory device with stacked dielectric structure including zirconium oxide and method for fabricating the same Oct 16, 2006 Issued
Array ( [id] => 5569884 [patent_doc_number] => 20090253262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'ELECTROLESS PLATING SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/549644 [patent_app_country] => US [patent_app_date] => 2006-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20090253262.pdf [firstpage_image] =>[orig_patent_app_number] => 11549644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/549644
Electroless plating system Oct 13, 2006 Issued
Array ( [id] => 303536 [patent_doc_number] => 07534672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-19 [patent_title] => 'Tiered gate device with source and drain extensions' [patent_app_type] => utility [patent_app_number] => 11/517791 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4291 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/534/07534672.pdf [firstpage_image] =>[orig_patent_app_number] => 11517791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/517791
Tiered gate device with source and drain extensions Sep 7, 2006 Issued
Array ( [id] => 43682 [patent_doc_number] => 07776705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Method for fabricating a thick copper line and copper inductor resulting therefrom' [patent_app_type] => utility [patent_app_number] => 11/470552 [patent_app_country] => US [patent_app_date] => 2006-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3619 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/776/07776705.pdf [firstpage_image] =>[orig_patent_app_number] => 11470552 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/470552
Method for fabricating a thick copper line and copper inductor resulting therefrom Sep 5, 2006 Issued
Array ( [id] => 4539403 [patent_doc_number] => 07875546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-25 [patent_title] => 'System and method for preventing metal corrosion on bond pads' [patent_app_type] => utility [patent_app_number] => 11/514621 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/875/07875546.pdf [firstpage_image] =>[orig_patent_app_number] => 11514621 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514621
System and method for preventing metal corrosion on bond pads Aug 31, 2006 Issued
Array ( [id] => 43822 [patent_doc_number] => 07776765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Tantalum silicon oxynitride high-k dielectrics and metal gates' [patent_app_type] => utility [patent_app_number] => 11/514601 [patent_app_country] => US [patent_app_date] => 2006-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 17294 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/776/07776765.pdf [firstpage_image] =>[orig_patent_app_number] => 11514601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/514601
Tantalum silicon oxynitride high-k dielectrics and metal gates Aug 30, 2006 Issued
Array ( [id] => 4999916 [patent_doc_number] => 20070042550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE HAVING SELECTIVE DOPANT REGIONS' [patent_app_type] => utility [patent_app_number] => 11/466259 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6025 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042550.pdf [firstpage_image] =>[orig_patent_app_number] => 11466259 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466259
Method for fabricating a semiconductor structure having selective dopant regions Aug 21, 2006 Issued
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