Search

Grant S. Withers

Examiner (ID: 18926, Phone: (571)270-1570 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2895, 2817, 2812, 2891
Total Applications
1000
Issued Applications
834
Pending Applications
38
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4909784 [patent_doc_number] => 20080020550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'PROCESS FOR MAKING THIN FILM FIELD EFFECT TRANSISTORS USING ZINC OXIDE' [patent_app_type] => utility [patent_app_number] => 11/458511 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4646 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20080020550.pdf [firstpage_image] =>[orig_patent_app_number] => 11458511 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/458511
Process for making thin film field effect transistors using zinc oxide Jul 18, 2006 Issued
Array ( [id] => 4803153 [patent_doc_number] => 20080014741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Process for improving the reliability of interconnect structures and resulting structure' [patent_app_type] => utility [patent_app_number] => 11/487741 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014741.pdf [firstpage_image] =>[orig_patent_app_number] => 11487741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/487741
Process for improving the reliability of interconnect structures and resulting structure Jul 16, 2006 Issued
Array ( [id] => 4514016 [patent_doc_number] => 07910420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-22 [patent_title] => 'System and method for improving CMOS compatible non volatile memory retention reliability' [patent_app_type] => utility [patent_app_number] => 11/486892 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4295 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/910/07910420.pdf [firstpage_image] =>[orig_patent_app_number] => 11486892 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486892
System and method for improving CMOS compatible non volatile memory retention reliability Jul 12, 2006 Issued
Array ( [id] => 4474679 [patent_doc_number] => 07867871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-11 [patent_title] => 'System and method for increasing breakdown voltage of LOCOS isolated devices' [patent_app_type] => utility [patent_app_number] => 11/486952 [patent_app_country] => US [patent_app_date] => 2006-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/867/07867871.pdf [firstpage_image] =>[orig_patent_app_number] => 11486952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486952
System and method for increasing breakdown voltage of LOCOS isolated devices Jul 12, 2006 Issued
Array ( [id] => 5075331 [patent_doc_number] => 20070015306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Manufacturing method of P type group III nitride semiconductor layer and light emitting device' [patent_app_type] => utility [patent_app_number] => 11/485232 [patent_app_country] => US [patent_app_date] => 2006-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4982 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20070015306.pdf [firstpage_image] =>[orig_patent_app_number] => 11485232 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485232
Manufacturing method of P type group III nitride semiconductor layer and light emitting device Jul 10, 2006 Abandoned
Array ( [id] => 4803152 [patent_doc_number] => 20080014740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)' [patent_app_type] => utility [patent_app_number] => 11/483901 [patent_app_country] => US [patent_app_date] => 2006-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014740.pdf [firstpage_image] =>[orig_patent_app_number] => 11483901 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/483901
Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) Jul 9, 2006 Issued
Array ( [id] => 4803096 [patent_doc_number] => 20080014684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Two-print-two-etch method for enhancement of CD control using ghost poly' [patent_app_type] => utility [patent_app_number] => 11/482041 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014684.pdf [firstpage_image] =>[orig_patent_app_number] => 11482041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482041
Two-print two-etch method for enhancement of CD control using ghost poly Jul 6, 2006 Issued
Array ( [id] => 4803144 [patent_doc_number] => 20080014732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'Application of PVD W/WN bilayer barrier to aluminum bondpad in wire bonding' [patent_app_type] => utility [patent_app_number] => 11/482522 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014732.pdf [firstpage_image] =>[orig_patent_app_number] => 11482522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482522
Application of PVD W/WN bilayer barrier to aluminum bondpad in wire bonding Jul 6, 2006 Abandoned
Array ( [id] => 5239783 [patent_doc_number] => 20070018274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Semiconductor circuit arrangement and method' [patent_app_type] => utility [patent_app_number] => 11/478912 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3113 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018274.pdf [firstpage_image] =>[orig_patent_app_number] => 11478912 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/478912
Semiconductor circuit arrangement and method Jun 29, 2006 Abandoned
Array ( [id] => 202542 [patent_doc_number] => 07632743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Method of manufacturing flash memory device' [patent_app_type] => utility [patent_app_number] => 11/479332 [patent_app_country] => US [patent_app_date] => 2006-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2326 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/632/07632743.pdf [firstpage_image] =>[orig_patent_app_number] => 11479332 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/479332
Method of manufacturing flash memory device Jun 29, 2006 Issued
Array ( [id] => 5834863 [patent_doc_number] => 20060246694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Laser thermal annealing of lightly doped silicon substrates' [patent_app_type] => utility [patent_app_number] => 11/478171 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8880 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20060246694.pdf [firstpage_image] =>[orig_patent_app_number] => 11478171 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/478171
Laser thermal annealing of lightly doped silicon substrates Jun 28, 2006 Issued
Array ( [id] => 5159951 [patent_doc_number] => 20070172995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method for forming fuse of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/474952 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1870 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20070172995.pdf [firstpage_image] =>[orig_patent_app_number] => 11474952 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/474952
Method for forming fuse of semiconductor device Jun 26, 2006 Abandoned
Array ( [id] => 5159989 [patent_doc_number] => 20070173033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method of fabricating a composite substrate with improved electrical properties' [patent_app_type] => utility [patent_app_number] => 11/473411 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20070173033.pdf [firstpage_image] =>[orig_patent_app_number] => 11473411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/473411
Method of fabricating a composite substrate with improved electrical properties Jun 22, 2006 Issued
Array ( [id] => 151498 [patent_doc_number] => 07682975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Semiconductor device fabrication method' [patent_app_type] => utility [patent_app_number] => 11/472462 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 38 [patent_no_of_words] => 11066 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/682/07682975.pdf [firstpage_image] =>[orig_patent_app_number] => 11472462 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/472462
Semiconductor device fabrication method Jun 21, 2006 Issued
Array ( [id] => 5599514 [patent_doc_number] => 20060289859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'METHOD FOR FORMING A STACKED STRUCTURE OF AN INSULATING LAYER AND AN ORGANIC SEMICONDUCTOR LAYER, ORGANIC FIELD EFFECT TRANSISTOR AND METHOD FOR MAKING SAME' [patent_app_type] => utility [patent_app_number] => 11/424672 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9181 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20060289859.pdf [firstpage_image] =>[orig_patent_app_number] => 11424672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/424672
Method for forming a stacked structure of an insulating layer and an organic semiconductor layer, organic field effect transistor and method for making same Jun 15, 2006 Issued
Array ( [id] => 5141834 [patent_doc_number] => 20070004050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method of regenerating substrate' [patent_app_type] => utility [patent_app_number] => 11/443091 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4419 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004050.pdf [firstpage_image] =>[orig_patent_app_number] => 11443091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/443091
Method of regenerating substrate May 30, 2006 Abandoned
Array ( [id] => 5884294 [patent_doc_number] => 20060273469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Carrier sheet with adhesive film and method for producing semiconductor devices using the carrier sheet with adhesive film' [patent_app_type] => utility [patent_app_number] => 11/439425 [patent_app_country] => US [patent_app_date] => 2006-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3401 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20060273469.pdf [firstpage_image] =>[orig_patent_app_number] => 11439425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/439425
Carrier sheet with adhesive film and method for producing semiconductor devices using the carrier sheet with adhesive film May 23, 2006 Issued
Array ( [id] => 8943984 [patent_doc_number] => 08497162 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-30 [patent_title] => 'Lid attach process' [patent_app_type] => utility [patent_app_number] => 11/379741 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3528 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11379741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/379741
Lid attach process Apr 20, 2006 Issued
Array ( [id] => 5670363 [patent_doc_number] => 20060175717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Semiconductor device and method of making the same' [patent_app_type] => utility [patent_app_number] => 11/399871 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3543 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20060175717.pdf [firstpage_image] =>[orig_patent_app_number] => 11399871 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/399871
Semiconductor device and method of making the same Apr 6, 2006 Abandoned
Array ( [id] => 5123053 [patent_doc_number] => 20070235322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Method for real-time monitoring the fabrication of magnetic memory units' [patent_app_type] => utility [patent_app_number] => 11/397638 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2182 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235322.pdf [firstpage_image] =>[orig_patent_app_number] => 11397638 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397638
Method for real-time monitoring the fabrication of magnetic memory units Apr 4, 2006 Abandoned
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