Grant S. Withers

Array ( [id] => 5683031 [patent_doc_number] => 20060199301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Methods of making a curable composition having low coefficient of thermal expansion and an integrated circuit and a curable composition and integrated circuit made there from' [patent_app_type] => utility [patent_app_number] => 11/317661 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11791 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199301.pdf [firstpage_image] =>[orig_patent_app_number] => 11317661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5645911 [patent_doc_number] => 20060131643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Semiconductor device and method of manufacturing the semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/313852 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1899 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20060131643.pdf [firstpage_image] =>[orig_patent_app_number] => 11313852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4557771 [patent_doc_number] => 07838367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Method for the manufacture of a semiconductor device and a semiconductor device obtained through it' [patent_app_type] => utility [patent_app_number] => 11/722988 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 34 [patent_no_of_words] => 3676 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838367.pdf [firstpage_image] =>[orig_patent_app_number] => 11722988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5631703 [patent_doc_number] => 20060148173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method for manufacturing electronic memory devices integrated in a semiconductor substrate including non-volatile memory matrix and associated circuitry' [patent_app_type] => utility [patent_app_number] => 11/302612 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2647 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148173.pdf [firstpage_image] =>[orig_patent_app_number] => 11302612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5141928 [patent_doc_number] => 20070004144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method of fabricating dual gate oxide layer having different thickness in the cell region and the peripheral region' [patent_app_type] => utility [patent_app_number] => 11/302812 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2117 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004144.pdf [firstpage_image] =>[orig_patent_app_number] => 11302812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5655969 [patent_doc_number] => 20060141705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Method for fabricating metal-insulator-metal capacitor of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/296511 [patent_app_country] => US [patent_app_date] => 2005-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2303 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141705.pdf [firstpage_image] =>[orig_patent_app_number] => 11296511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5628822 [patent_doc_number] => 20060145290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type' [patent_app_type] => utility [patent_app_number] => 11/294411 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8275 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145290.pdf [firstpage_image] =>[orig_patent_app_number] => 11294411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5908926 [patent_doc_number] => 20060125000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Field effect transistor and fabrication method' [patent_app_type] => utility [patent_app_number] => 11/295152 [patent_app_country] => US [patent_app_date] => 2005-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4165 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20060125000.pdf [firstpage_image] =>[orig_patent_app_number] => 11295152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5705341 [patent_doc_number] => 20060194389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Method for fabricating flash memory device' [patent_app_type] => utility [patent_app_number] => 11/292461 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1967 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20060194389.pdf [firstpage_image] =>[orig_patent_app_number] => 11292461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5805070 [patent_doc_number] => 20060091422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Semiconductor memory and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/291342 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3433 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091422.pdf [firstpage_image] =>[orig_patent_app_number] => 11291342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5908899 [patent_doc_number] => 20060124988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Methods of fabricating flash memory devices having self-aligned floating gate electrodes and related devices' [patent_app_type] => utility [patent_app_number] => 11/291142 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10264 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20060124988.pdf [firstpage_image] =>[orig_patent_app_number] => 11291142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5145797 [patent_doc_number] => 20070045851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Manufacture method for semiconductor device suitable for forming wirings by damascene method and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/289512 [patent_app_country] => US [patent_app_date] => 2005-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5635 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045851.pdf [firstpage_image] =>[orig_patent_app_number] => 11289512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5079696 [patent_doc_number] => 20070122920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Method for improved control of critical dimensions of etched structures on semiconductor wafers' [patent_app_type] => utility [patent_app_number] => 11/289074 [patent_app_country] => US [patent_app_date] => 2005-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20070122920.pdf [firstpage_image] =>[orig_patent_app_number] => 11289074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4971447 [patent_doc_number] => 20070111449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Non-volatile memory cell and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/281272 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3591 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111449.pdf [firstpage_image] =>[orig_patent_app_number] => 11281272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 856737 [patent_doc_number] => 07374996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Structured, electrically-formed floating gate for flash memories' [patent_app_type] => utility [patent_app_number] => 11/274622 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 6800 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/374/07374996.pdf [firstpage_image] =>[orig_patent_app_number] => 11274622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8028061 [patent_doc_number] => 08143111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'System and method for configuring an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/273909 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5630 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/143/08143111.pdf [firstpage_image] =>[orig_patent_app_number] => 11273909 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5205134 [patent_doc_number] => 20070026616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Method for fabricating semiconductor device and semiconductor device fabricated using the same' [patent_app_type] => utility [patent_app_number] => 11/272568 [patent_app_country] => US [patent_app_date] => 2005-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2942 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026616.pdf [firstpage_image] =>[orig_patent_app_number] => 11272568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5889108 [patent_doc_number] => 20060275947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Process for forming an electronic device including reflowing a conductive member' [patent_app_type] => utility [patent_app_number] => 11/270012 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 20357 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20060275947.pdf [firstpage_image] =>[orig_patent_app_number] => 11270012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5141840 [patent_doc_number] => 20070004056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Systems and methods for direct silicon epitaxy thickness measuring' [patent_app_type] => utility [patent_app_number] => 11/269302 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20070004056.pdf [firstpage_image] =>[orig_patent_app_number] => 11269302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5828316 [patent_doc_number] => 20060063340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Collector layer structure for a double hetero-junction bipolar transistor for power amplification applications' [patent_app_type] => utility [patent_app_number] => 11/268119 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4792 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20060063340.pdf [firstpage_image] =>[orig_patent_app_number] => 11268119 [rel_patent_id] =>[rel_patent_doc_number] =>)