Search

Grant S. Withers

Examiner (ID: 18926, Phone: (571)270-1570 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2895, 2817, 2812, 2891
Total Applications
1000
Issued Applications
834
Pending Applications
38
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 891870 [patent_doc_number] => 07344926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Liquid crystal display device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/267335 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6153 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/344/07344926.pdf [firstpage_image] =>[orig_patent_app_number] => 11267335 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267335
Liquid crystal display device and method of manufacturing the same Nov 6, 2005 Issued
Array ( [id] => 5611660 [patent_doc_number] => 20060113584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Manufacturing method of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/267582 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5457 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20060113584.pdf [firstpage_image] =>[orig_patent_app_number] => 11267582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267582
Manufacturing method of a semiconductor device Nov 6, 2005 Abandoned
Array ( [id] => 7689371 [patent_doc_number] => 20070105327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Methods of forming field effect transistors using disposable aluminum oxide spacers' [patent_app_type] => utility [patent_app_number] => 11/268132 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2101 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20070105327.pdf [firstpage_image] =>[orig_patent_app_number] => 11268132 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268132
Methods of forming field effect transistors using disposable aluminum oxide spacers Nov 6, 2005 Issued
Array ( [id] => 557379 [patent_doc_number] => 07470578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Method of making a finFET having suppressed parasitic device characteristics' [patent_app_type] => utility [patent_app_number] => 11/267882 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/470/07470578.pdf [firstpage_image] =>[orig_patent_app_number] => 11267882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267882
Method of making a finFET having suppressed parasitic device characteristics Nov 3, 2005 Issued
Array ( [id] => 168175 [patent_doc_number] => 07666736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Method for fabricating semiconductor device comprising P-type MISFET, including step of implanting fluorine' [patent_app_type] => utility [patent_app_number] => 11/265102 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 25 [patent_no_of_words] => 9282 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/666/07666736.pdf [firstpage_image] =>[orig_patent_app_number] => 11265102 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265102
Method for fabricating semiconductor device comprising P-type MISFET, including step of implanting fluorine Nov 2, 2005 Issued
Array ( [id] => 5031780 [patent_doc_number] => 20070096319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions' [patent_app_type] => utility [patent_app_number] => 11/266741 [patent_app_country] => US [patent_app_date] => 2005-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2616 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096319.pdf [firstpage_image] =>[orig_patent_app_number] => 11266741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/266741
Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions Nov 2, 2005 Issued
Array ( [id] => 5805149 [patent_doc_number] => 20060091502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Multilayer structure comprising a substrate and a layer of silicon and germanium deposited heteroepitaxially thereon, and a process for producing it' [patent_app_type] => utility [patent_app_number] => 11/263192 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091502.pdf [firstpage_image] =>[orig_patent_app_number] => 11263192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263192
Multilayer structure comprising a substrate and a layer of silicon and germanium deposited heteroepitaxially thereon, and a process for producing it Oct 30, 2005 Issued
Array ( [id] => 5034896 [patent_doc_number] => 20070099435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method and system for forming a nitrided germanium-containing layer using plasma processing' [patent_app_type] => utility [patent_app_number] => 11/263402 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9178 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20070099435.pdf [firstpage_image] =>[orig_patent_app_number] => 11263402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/263402
Method and system for forming a nitrided germanium-containing layer using plasma processing Oct 30, 2005 Issued
Array ( [id] => 5864355 [patent_doc_number] => 20060098485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Printable non-volatile passive memory element and method of making thereof' [patent_app_type] => utility [patent_app_number] => 11/260832 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 13309 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20060098485.pdf [firstpage_image] =>[orig_patent_app_number] => 11260832 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260832
Printable non-volatile passive memory element and method of making thereof Oct 26, 2005 Abandoned
Array ( [id] => 823573 [patent_doc_number] => 07405133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-29 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/256929 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 56 [patent_no_of_words] => 6755 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/405/07405133.pdf [firstpage_image] =>[orig_patent_app_number] => 11256929 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256929
Semiconductor device and method for manufacturing the same Oct 24, 2005 Issued
Array ( [id] => 5743263 [patent_doc_number] => 20060088988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Method for forming silicon-germanium in the upper portion of a silicon substrate' [patent_app_type] => utility [patent_app_number] => 11/258402 [patent_app_country] => US [patent_app_date] => 2005-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2700 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20060088988.pdf [firstpage_image] =>[orig_patent_app_number] => 11258402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/258402
Method for forming silicon-germanium in the upper portion of a silicon substrate Oct 24, 2005 Abandoned
Array ( [id] => 5040785 [patent_doc_number] => 20070093067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Wafer edge cleaning process' [patent_app_type] => utility [patent_app_number] => 11/256711 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20070093067.pdf [firstpage_image] =>[orig_patent_app_number] => 11256711 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256711
Wafer edge cleaning process Oct 23, 2005 Abandoned
Array ( [id] => 295971 [patent_doc_number] => 07541240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Integration process flow for flash devices with low gap fill aspect ratio' [patent_app_type] => utility [patent_app_number] => 11/254142 [patent_app_country] => US [patent_app_date] => 2005-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8921 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/541/07541240.pdf [firstpage_image] =>[orig_patent_app_number] => 11254142 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254142
Integration process flow for flash devices with low gap fill aspect ratio Oct 17, 2005 Issued
Array ( [id] => 876093 [patent_doc_number] => 07358143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/250392 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 38 [patent_no_of_words] => 9577 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/358/07358143.pdf [firstpage_image] =>[orig_patent_app_number] => 11250392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/250392
Semiconductor device Oct 16, 2005 Issued
Array ( [id] => 5810794 [patent_doc_number] => 20060081902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Ferroelectric memory and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/252316 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5085 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20060081902.pdf [firstpage_image] =>[orig_patent_app_number] => 11252316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252316
Ferroelectric memory and method of manufacturing the same Oct 16, 2005 Abandoned
Array ( [id] => 4982945 [patent_doc_number] => 20070087503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Improving NROM device characteristics using adjusted gate work function' [patent_app_type] => utility [patent_app_number] => 11/253272 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2216 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20070087503.pdf [firstpage_image] =>[orig_patent_app_number] => 11253272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/253272
Improving NROM device characteristics using adjusted gate work function Oct 16, 2005 Abandoned
Array ( [id] => 217074 [patent_doc_number] => 07611984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-03 [patent_title] => 'Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy' [patent_app_type] => utility [patent_app_number] => 11/249442 [patent_app_country] => US [patent_app_date] => 2005-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 9301 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/611/07611984.pdf [firstpage_image] =>[orig_patent_app_number] => 11249442 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/249442
Manufacture method for semiconductor device having improved copper diffusion preventive function of plugs and wirings made of copper or copper alloy Oct 13, 2005 Issued
Array ( [id] => 864607 [patent_doc_number] => 07368348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Methods of forming MOS transistors having buried gate electrodes therein' [patent_app_type] => utility [patent_app_number] => 11/246401 [patent_app_country] => US [patent_app_date] => 2005-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 45 [patent_no_of_words] => 4445 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/368/07368348.pdf [firstpage_image] =>[orig_patent_app_number] => 11246401 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/246401
Methods of forming MOS transistors having buried gate electrodes therein Oct 6, 2005 Issued
Array ( [id] => 5193993 [patent_doc_number] => 20070082477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Integrated circuit fabricating techniques employing sacrificial liners' [patent_app_type] => utility [patent_app_number] => 11/245712 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11617 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20070082477.pdf [firstpage_image] =>[orig_patent_app_number] => 11245712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/245712
Integrated circuit fabricating techniques employing sacrificial liners Oct 5, 2005 Abandoned
Array ( [id] => 5136052 [patent_doc_number] => 20070077681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Liquid phase fabrication of active devices including organic semiconductors' [patent_app_type] => utility [patent_app_number] => 11/240222 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20070077681.pdf [firstpage_image] =>[orig_patent_app_number] => 11240222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/240222
Liquid phase fabrication of active devices including organic semiconductors Sep 29, 2005 Issued
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