Search

Granvill D. Lee

Examiner (ID: 12333)

Most Active Art Unit
2825
Art Unit(s)
2825, 2891, 2829
Total Applications
333
Issued Applications
315
Pending Applications
6
Abandoned Applications
12

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1228286 [patent_doc_number] => 06696362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Method for using an in situ particle sensor for monitoring particle performance in plasma deposition processes' [patent_app_type] => B2 [patent_app_number] => 10/122058 [patent_app_country] => US [patent_app_date] => 2002-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9538 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696362.pdf [firstpage_image] =>[orig_patent_app_number] => 10122058 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/122058
Method for using an in situ particle sensor for monitoring particle performance in plasma deposition processes Apr 11, 2002 Issued
Array ( [id] => 7287306 [patent_doc_number] => 20040147102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Production method for a semiconductor component' [patent_app_type] => new [patent_app_number] => 10/477620 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1768 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147102.pdf [firstpage_image] =>[orig_patent_app_number] => 10477620 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/477620
Production method for a semiconductor component Apr 10, 2002 Issued
Array ( [id] => 1073666 [patent_doc_number] => 06838331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Method and system for dynamically operating memory in a power-saving error correction mode' [patent_app_type] => utility [patent_app_number] => 10/119550 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5809 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838331.pdf [firstpage_image] =>[orig_patent_app_number] => 10119550 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/119550
Method and system for dynamically operating memory in a power-saving error correction mode Apr 8, 2002 Issued
Array ( [id] => 6797172 [patent_doc_number] => 20030176046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Method for tiling unit cells' [patent_app_type] => new [patent_app_number] => 10/099140 [patent_app_country] => US [patent_app_date] => 2002-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18306 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20030176046.pdf [firstpage_image] =>[orig_patent_app_number] => 10099140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/099140
Method for tiling unit cells Mar 15, 2002 Issued
Array ( [id] => 6408256 [patent_doc_number] => 20020182761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method of manufacturing field-emission electron emitters and method of manufacturing substrates having a matrix electron emitter array formed thereon' [patent_app_type] => new [patent_app_number] => 10/092440 [patent_app_country] => US [patent_app_date] => 2002-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182761.pdf [firstpage_image] =>[orig_patent_app_number] => 10092440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092440
Method of manufacturing field-emission electron emitters and method of manufacturing substrates having a matrix electron emitter array formed thereon Mar 7, 2002 Issued
Array ( [id] => 1361535 [patent_doc_number] => 06569730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'High voltage transistor using P buried layer' [patent_app_type] => B2 [patent_app_number] => 10/091990 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2163 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569730.pdf [firstpage_image] =>[orig_patent_app_number] => 10091990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/091990
High voltage transistor using P buried layer Mar 5, 2002 Issued
Array ( [id] => 1261477 [patent_doc_number] => 06664167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Memory with trench capacitor and selection transistor and method for fabricating it' [patent_app_type] => B2 [patent_app_number] => 10/085940 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7711 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664167.pdf [firstpage_image] =>[orig_patent_app_number] => 10085940 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/085940
Memory with trench capacitor and selection transistor and method for fabricating it Feb 27, 2002 Issued
Array ( [id] => 1292486 [patent_doc_number] => 06643834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method of and apparatus for designing layout of analog cells, and computer product' [patent_app_type] => B2 [patent_app_number] => 10/080044 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 38 [patent_no_of_words] => 14745 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643834.pdf [firstpage_image] =>[orig_patent_app_number] => 10080044 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/080044
Method of and apparatus for designing layout of analog cells, and computer product Feb 21, 2002 Issued
Array ( [id] => 975620 [patent_doc_number] => 06938224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Method for modeling noise emitted by digital circuits' [patent_app_type] => utility [patent_app_number] => 10/079447 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3060 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/938/06938224.pdf [firstpage_image] =>[orig_patent_app_number] => 10079447 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/079447
Method for modeling noise emitted by digital circuits Feb 19, 2002 Issued
Array ( [id] => 1037489 [patent_doc_number] => 06872638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/078240 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 52 [patent_no_of_words] => 17860 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872638.pdf [firstpage_image] =>[orig_patent_app_number] => 10078240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/078240
Method of manufacturing a semiconductor device Feb 19, 2002 Issued
Array ( [id] => 1177591 [patent_doc_number] => 06743729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Etching method and etching apparatus of carbon thin film' [patent_app_type] => B2 [patent_app_number] => 10/076360 [patent_app_country] => US [patent_app_date] => 2002-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2997 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/743/06743729.pdf [firstpage_image] =>[orig_patent_app_number] => 10076360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076360
Etching method and etching apparatus of carbon thin film Feb 18, 2002 Issued
Array ( [id] => 1378393 [patent_doc_number] => 06555402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Self-aligned field extraction grid and method of forming' [patent_app_type] => B2 [patent_app_number] => 10/071440 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3847 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555402.pdf [firstpage_image] =>[orig_patent_app_number] => 10071440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/071440
Self-aligned field extraction grid and method of forming Feb 7, 2002 Issued
Array ( [id] => 1180164 [patent_doc_number] => 06740603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Control of Vmin transient voltage drift by maintaining a temperature less than or equal to 350 C. after the protective overcoat level' [patent_app_type] => B2 [patent_app_number] => 10/061650 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1476 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740603.pdf [firstpage_image] =>[orig_patent_app_number] => 10061650 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061650
Control of Vmin transient voltage drift by maintaining a temperature less than or equal to 350 C. after the protective overcoat level Jan 31, 2002 Issued
Array ( [id] => 6016464 [patent_doc_number] => 20020102828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method for manufacturing a semiconductor circuit system' [patent_app_type] => new [patent_app_number] => 10/062940 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4047 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102828.pdf [firstpage_image] =>[orig_patent_app_number] => 10062940 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/062940
Method for manufacturing a semiconductor circuit system Jan 30, 2002 Issued
Array ( [id] => 6158053 [patent_doc_number] => 20020146883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/042140 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5683 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20020146883.pdf [firstpage_image] =>[orig_patent_app_number] => 10042140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042140
Semiconductor devices having a non-volatile memory transistor and methods for manufacturing the same Jan 10, 2002 Issued
Array ( [id] => 1050050 [patent_doc_number] => 06861327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Method for manufacturing gate spacer for self-aligned contact' [patent_app_type] => utility [patent_app_number] => 10/044799 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1883 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861327.pdf [firstpage_image] =>[orig_patent_app_number] => 10044799 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044799
Method for manufacturing gate spacer for self-aligned contact Jan 9, 2002 Issued
Array ( [id] => 1101532 [patent_doc_number] => 06815230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Control signal transmitting method with package power pin and related integrated circuit package structure' [patent_app_type] => B2 [patent_app_number] => 10/034320 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2234 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815230.pdf [firstpage_image] =>[orig_patent_app_number] => 10034320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034320
Control signal transmitting method with package power pin and related integrated circuit package structure Dec 27, 2001 Issued
Array ( [id] => 6571046 [patent_doc_number] => 20020084470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Semiconductor device and semiconductor device assembly' [patent_app_type] => new [patent_app_number] => 10/012540 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1653 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084470.pdf [firstpage_image] =>[orig_patent_app_number] => 10012540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/012540
Semiconductor device and semiconductor device assembly Dec 11, 2001 Issued
Array ( [id] => 7634867 [patent_doc_number] => 06656751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Self test method and device for dynamic voltage screen functionality improvement' [patent_app_type] => B2 [patent_app_number] => 09/683050 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2687 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656751.pdf [firstpage_image] =>[orig_patent_app_number] => 09683050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683050
Self test method and device for dynamic voltage screen functionality improvement Nov 12, 2001 Issued
Array ( [id] => 1302999 [patent_doc_number] => 06620712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Defined sacrifical region via ion implantation for micro-opto-electro-mechanical system (MOEMS) applications' [patent_app_type] => B2 [patent_app_number] => 10/011350 [patent_app_country] => US [patent_app_date] => 2001-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 31 [patent_no_of_words] => 2972 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/620/06620712.pdf [firstpage_image] =>[orig_patent_app_number] => 10011350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011350
Defined sacrifical region via ion implantation for micro-opto-electro-mechanical system (MOEMS) applications Nov 11, 2001 Issued
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