Search

Granvill D. Lee

Examiner (ID: 12333)

Most Active Art Unit
2825
Art Unit(s)
2825, 2891, 2829
Total Applications
333
Issued Applications
315
Pending Applications
6
Abandoned Applications
12

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1288841 [patent_doc_number] => 06632733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Components and methods with nested leads' [patent_app_type] => B2 [patent_app_number] => 09/808461 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8594 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632733.pdf [firstpage_image] =>[orig_patent_app_number] => 09808461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808461
Components and methods with nested leads Mar 13, 2001 Issued
Array ( [id] => 1335952 [patent_doc_number] => 06593175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method of controlling a shape of an oxide layer formed on a substrate' [patent_app_type] => B2 [patent_app_number] => 09/809710 [patent_app_country] => US [patent_app_date] => 2001-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 4074 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593175.pdf [firstpage_image] =>[orig_patent_app_number] => 09809710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809710
Method of controlling a shape of an oxide layer formed on a substrate Mar 13, 2001 Issued
Array ( [id] => 6367785 [patent_doc_number] => 20020117951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Carbon tips with expanded bases' [patent_app_type] => new [patent_app_number] => 09/795660 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4625 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20020117951.pdf [firstpage_image] =>[orig_patent_app_number] => 09795660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795660
Carbon tips with expanded bases grown with simultaneous application of carbon source and etchant gases Feb 26, 2001 Issued
Array ( [id] => 1370828 [patent_doc_number] => 06562633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Assembling arrays of small particles using an atomic force microscope to define ferroelectric domains' [patent_app_type] => B2 [patent_app_number] => 09/791640 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2735 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562633.pdf [firstpage_image] =>[orig_patent_app_number] => 09791640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791640
Assembling arrays of small particles using an atomic force microscope to define ferroelectric domains Feb 25, 2001 Issued
Array ( [id] => 1378583 [patent_doc_number] => 06555413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method for interconnecting semiconductor elements to form a thermoelectric cooler and a thermoelectric cooler formed therefrom' [patent_app_type] => B1 [patent_app_number] => 09/790810 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555413.pdf [firstpage_image] =>[orig_patent_app_number] => 09790810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790810
Method for interconnecting semiconductor elements to form a thermoelectric cooler and a thermoelectric cooler formed therefrom Feb 22, 2001 Issued
Array ( [id] => 1340090 [patent_doc_number] => 06589868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Si seasoning to reduce particles, extend clean frequency, block mobile ions and increase chamber throughput' [patent_app_type] => B2 [patent_app_number] => 09/780800 [patent_app_country] => US [patent_app_date] => 2001-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7903 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/589/06589868.pdf [firstpage_image] =>[orig_patent_app_number] => 09780800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780800
Si seasoning to reduce particles, extend clean frequency, block mobile ions and increase chamber throughput Feb 7, 2001 Issued
Array ( [id] => 6894037 [patent_doc_number] => 20010016403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Semiconductor substrate with semi-insulating polysilicon gettering site layer and process of fabrication thereof' [patent_app_type] => new [patent_app_number] => 09/772972 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3873 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20010016403.pdf [firstpage_image] =>[orig_patent_app_number] => 09772972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772972
Semiconductor substrate with semi-insulating polysilicon gettering site layer and process of fabrication thereof Jan 30, 2001 Abandoned
Array ( [id] => 1595678 [patent_doc_number] => 06492254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Ball grid array (BGA) to column grid array (CGA) conversion process' [patent_app_type] => B2 [patent_app_number] => 09/774010 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492254.pdf [firstpage_image] =>[orig_patent_app_number] => 09774010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774010
Ball grid array (BGA) to column grid array (CGA) conversion process Jan 30, 2001 Issued
Array ( [id] => 1478847 [patent_doc_number] => 06344670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-05 [patent_title] => 'Solid-state sensor and system' [patent_app_type] => B2 [patent_app_number] => 09/755117 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 14206 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344670.pdf [firstpage_image] =>[orig_patent_app_number] => 09755117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755117
Solid-state sensor and system Jan 7, 2001 Issued
Array ( [id] => 1323913 [patent_doc_number] => 06602728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Method for generating a proximity model based on proximity rules' [patent_app_type] => B1 [patent_app_number] => 09/754920 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4174 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602728.pdf [firstpage_image] =>[orig_patent_app_number] => 09754920 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754920
Method for generating a proximity model based on proximity rules Jan 4, 2001 Issued
Array ( [id] => 6885856 [patent_doc_number] => 20010019125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/751840 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 9647 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019125.pdf [firstpage_image] =>[orig_patent_app_number] => 09751840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751840
Contact structures of wirings and methods for manufacturing the same, and thin film transistor array panels including the same and methods for manufacturing the same Jan 1, 2001 Issued
Array ( [id] => 1310714 [patent_doc_number] => 06613654 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Fabrication of semiconductor devices with transition metal boride films as diffusion barriers' [patent_app_type] => B1 [patent_app_number] => 09/739270 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2575 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613654.pdf [firstpage_image] =>[orig_patent_app_number] => 09739270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739270
Fabrication of semiconductor devices with transition metal boride films as diffusion barriers Dec 18, 2000 Issued
Array ( [id] => 1514464 [patent_doc_number] => 06420219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-16 [patent_title] => 'Thin film transistors and method of forming thin film transistors' [patent_app_type] => B2 [patent_app_number] => 09/742149 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3813 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420219.pdf [firstpage_image] =>[orig_patent_app_number] => 09742149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/742149
Thin film transistors and method of forming thin film transistors Dec 14, 2000 Issued
Array ( [id] => 6892807 [patent_doc_number] => 20010015173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Method for forming a thin film of a composite metal compound and apparatus for carrying out the method' [patent_app_type] => new [patent_app_number] => 09/730564 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7258 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015173.pdf [firstpage_image] =>[orig_patent_app_number] => 09730564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/730564
Method for forming a thin film of a composite metal compound and apparatus for carrying out the method Dec 6, 2000 Issued
Array ( [id] => 1576351 [patent_doc_number] => 06447633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Reactor for processing a semiconductor wafer' [patent_app_type] => B1 [patent_app_number] => 09/710530 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 12490 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/447/06447633.pdf [firstpage_image] =>[orig_patent_app_number] => 09710530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/710530
Reactor for processing a semiconductor wafer Nov 8, 2000 Issued
Array ( [id] => 1500233 [patent_doc_number] => 06486011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'JFET structure and manufacture method for low on-resistance and low voltage application' [patent_app_type] => B1 [patent_app_number] => 09/690703 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 5274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486011.pdf [firstpage_image] =>[orig_patent_app_number] => 09690703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/690703
JFET structure and manufacture method for low on-resistance and low voltage application Oct 15, 2000 Issued
Array ( [id] => 1104752 [patent_doc_number] => 06812060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards' [patent_app_type] => B1 [patent_app_number] => 09/688181 [patent_app_country] => US [patent_app_date] => 2000-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 4693 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812060.pdf [firstpage_image] =>[orig_patent_app_number] => 09688181 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/688181
Multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards Oct 15, 2000 Issued
Array ( [id] => 1192907 [patent_doc_number] => 06730544 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Stackable semiconductor package and method for manufacturing same' [patent_app_type] => B1 [patent_app_number] => 09/687530 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5261 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730544.pdf [firstpage_image] =>[orig_patent_app_number] => 09687530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/687530
Stackable semiconductor package and method for manufacturing same Oct 12, 2000 Issued
Array ( [id] => 1256158 [patent_doc_number] => 06667237 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Method and apparatus for patterning fine dimensions' [patent_app_type] => B1 [patent_app_number] => 09/689074 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 37 [patent_no_of_words] => 4326 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667237.pdf [firstpage_image] =>[orig_patent_app_number] => 09689074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689074
Method and apparatus for patterning fine dimensions Oct 11, 2000 Issued
Array ( [id] => 1397258 [patent_doc_number] => 06531395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method for fabricating bitlines' [patent_app_type] => B1 [patent_app_number] => 09/686311 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2005 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531395.pdf [firstpage_image] =>[orig_patent_app_number] => 09686311 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/686311
Method for fabricating bitlines Oct 10, 2000 Issued
Menu