
Granvill D. Lee
Examiner (ID: 12333)
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2825, 2891, 2829 |
| Total Applications | 333 |
| Issued Applications | 315 |
| Pending Applications | 6 |
| Abandoned Applications | 12 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1467039
[patent_doc_number] => 06458687
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Method for forming conductive structures'
[patent_app_type] => B1
[patent_app_number] => 09/638227
[patent_app_country] => US
[patent_app_date] => 2000-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 9322
[patent_no_of_claims] => 34
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[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/458/06458687.pdf
[firstpage_image] =>[orig_patent_app_number] => 09638227
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/638227 | Method for forming conductive structures | Aug 13, 2000 | Issued |
Array
(
[id] => 1580909
[patent_doc_number] => 06423555
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'System for determining overlay error'
[patent_app_type] => B1
[patent_app_number] => 09/633441
[patent_app_country] => US
[patent_app_date] => 2000-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 4897
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[patent_words_short_claim] => 113
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/423/06423555.pdf
[firstpage_image] =>[orig_patent_app_number] => 09633441
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/633441 | System for determining overlay error | Aug 6, 2000 | Issued |
| 09/621550 | Pulse laser irradiation method for forming a semiconductor thin film | Jul 20, 2000 | Abandoned |
Array
(
[id] => 1297602
[patent_doc_number] => 06627548
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Process for treating semiconductor substrates'
[patent_app_type] => B1
[patent_app_number] => 09/617500
[patent_app_country] => US
[patent_app_date] => 2000-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
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[patent_no_of_words] => 2728
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/617500 | Process for treating semiconductor substrates | Jul 16, 2000 | Issued |
Array
(
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[patent_doc_number] => 06372661
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[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Method to improve the crack resistance of CVD low-k dielectric constant material'
[patent_app_type] => B1
[patent_app_number] => 09/617011
[patent_app_country] => US
[patent_app_date] => 2000-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4164
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[pdf_file] => patents/06/372/06372661.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/617011 | Method to improve the crack resistance of CVD low-k dielectric constant material | Jul 13, 2000 | Issued |
Array
(
[id] => 1245731
[patent_doc_number] => 06677225
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[patent_issue_date] => 2004-01-13
[patent_title] => 'System and method for constraining totally released microcomponents'
[patent_app_type] => B1
[patent_app_number] => 09/616500
[patent_app_country] => US
[patent_app_date] => 2000-07-14
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[pdf_file] => patents/06/677/06677225.pdf
[firstpage_image] =>[orig_patent_app_number] => 09616500
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/616500 | System and method for constraining totally released microcomponents | Jul 13, 2000 | Issued |
Array
(
[id] => 1467097
[patent_doc_number] => 06458717
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Methods of forming ultra-thin buffer oxide layers for gate dielectrics'
[patent_app_type] => B1
[patent_app_number] => 09/615810
[patent_app_country] => US
[patent_app_date] => 2000-07-13
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[pdf_file] => patents/06/458/06458717.pdf
[firstpage_image] =>[orig_patent_app_number] => 09615810
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/615810 | Methods of forming ultra-thin buffer oxide layers for gate dielectrics | Jul 12, 2000 | Issued |
Array
(
[id] => 1417662
[patent_doc_number] => 06514785
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'CMOS image sensor n-type pin-diode structure'
[patent_app_type] => B1
[patent_app_number] => 09/590125
[patent_app_country] => US
[patent_app_date] => 2000-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2151
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[pdf_file] => patents/06/514/06514785.pdf
[firstpage_image] =>[orig_patent_app_number] => 09590125
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/590125 | CMOS image sensor n-type pin-diode structure | Jun 8, 2000 | Issued |
Array
(
[id] => 1034431
[patent_doc_number] => 06875640
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-05
[patent_title] => 'Stereolithographic methods for forming a protective layer on a semiconductor device substrate and substrates including protective layers so formed'
[patent_app_type] => utility
[patent_app_number] => 09/589841
[patent_app_country] => US
[patent_app_date] => 2000-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 8768
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[pdf_file] => patents/06/875/06875640.pdf
[firstpage_image] =>[orig_patent_app_number] => 09589841
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/589841 | Stereolithographic methods for forming a protective layer on a semiconductor device substrate and substrates including protective layers so formed | Jun 7, 2000 | Issued |
Array
(
[id] => 1517301
[patent_doc_number] => 06500737
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-31
[patent_title] => 'System and method for providing defect free rapid thermal processing'
[patent_app_type] => B1
[patent_app_number] => 09/589851
[patent_app_country] => US
[patent_app_date] => 2000-06-08
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[pdf_file] => patents/06/500/06500737.pdf
[firstpage_image] =>[orig_patent_app_number] => 09589851
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/589851 | System and method for providing defect free rapid thermal processing | Jun 7, 2000 | Issued |
Array
(
[id] => 1559699
[patent_doc_number] => 06436764
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-20
[patent_title] => 'Method for manufacturing a flash memory with split gate cells'
[patent_app_type] => B1
[patent_app_number] => 09/590721
[patent_app_country] => US
[patent_app_date] => 2000-06-08
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[pdf_file] => patents/06/436/06436764.pdf
[firstpage_image] =>[orig_patent_app_number] => 09590721
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/590721 | Method for manufacturing a flash memory with split gate cells | Jun 7, 2000 | Issued |
Array
(
[id] => 4405071
[patent_doc_number] => 06271114
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'System for adjusting the size of conductive lines based upon the contact size'
[patent_app_type] => 1
[patent_app_number] => 9/587809
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[patent_app_date] => 2000-06-06
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/587809 | System for adjusting the size of conductive lines based upon the contact size | Jun 5, 2000 | Issued |
Array
(
[id] => 1495060
[patent_doc_number] => 06403475
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[patent_issue_date] => 2002-06-11
[patent_title] => 'Fabrication method for semiconductor integrated device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/588082 | Fabrication method for semiconductor integrated device | Jun 5, 2000 | Issued |
Array
(
[id] => 7645736
[patent_doc_number] => 06472233
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[patent_issue_date] => 2002-10-29
[patent_title] => 'MOSFET test structure for capacitance-voltage measurements'
[patent_app_type] => B1
[patent_app_number] => 09/586960
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/586960 | MOSFET test structure for capacitance-voltage measurements | Jun 4, 2000 | Issued |
Array
(
[id] => 1379023
[patent_doc_number] => 06555440
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[patent_issue_date] => 2003-04-29
[patent_title] => 'Process for fabricating a top side pitted diode device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/587720 | Process for fabricating a top side pitted diode device | Jun 4, 2000 | Issued |
Array
(
[id] => 4324502
[patent_doc_number] => 06329231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-11
[patent_title] => 'Distributed constant circuit with active element'
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[patent_app_number] => 9/579271
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/579271 | Distributed constant circuit with active element | May 25, 2000 | Issued |
Array
(
[id] => 1477557
[patent_doc_number] => 06344365
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-05
[patent_title] => 'Arc coating on mask quartz plate to avoid alignment error on stepper or scanner'
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[patent_app_number] => 09/578411
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/578411 | Arc coating on mask quartz plate to avoid alignment error on stepper or scanner | May 25, 2000 | Issued |
Array
(
[id] => 7640261
[patent_doc_number] => 06395653
[patent_country] => US
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[patent_issue_date] => 2002-05-28
[patent_title] => 'Semiconductor wafer with crystal lattice defects, and process for producing this wafer'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/554161 | Layered product, capacitor and a method for producing the layered product | May 9, 2000 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/560970 | Interposers including upwardly protruding dams, semiconductor device assemblies including the interposers, and methods | Apr 27, 2000 | Issued |