Search

Gregory A. Anderson

Examiner (ID: 3781, Phone: (571)270-3083 , Office: P/3731 )

Most Active Art Unit
3773
Art Unit(s)
3700, 3773, 3731, 3771, 3709, 4138
Total Applications
754
Issued Applications
532
Pending Applications
44
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4374269 [patent_doc_number] => 06256254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Semiconductor memory device decoder' [patent_app_type] => 1 [patent_app_number] => 9/564593 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5469 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256254.pdf [firstpage_image] =>[orig_patent_app_number] => 564593 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564593
Semiconductor memory device decoder May 2, 2000 Issued
Array ( [id] => 1493353 [patent_doc_number] => 06418056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method and apparatus for a voltage responsive reset for EEPROM' [patent_app_type] => B1 [patent_app_number] => 09/563197 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3507 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418056.pdf [firstpage_image] =>[orig_patent_app_number] => 09563197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/563197
Method and apparatus for a voltage responsive reset for EEPROM May 1, 2000 Issued
Array ( [id] => 4363460 [patent_doc_number] => 06215694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Self-restoring single event upset (SEU) hardened multiport memory cell' [patent_app_type] => 1 [patent_app_number] => 9/553595 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3260 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215694.pdf [firstpage_image] =>[orig_patent_app_number] => 553595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/553595
Self-restoring single event upset (SEU) hardened multiport memory cell Apr 19, 2000 Issued
Array ( [id] => 4395311 [patent_doc_number] => 06278640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Dynamic memory word line driver scheme' [patent_app_type] => 1 [patent_app_number] => 9/548879 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1721 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278640.pdf [firstpage_image] =>[orig_patent_app_number] => 548879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/548879
Dynamic memory word line driver scheme Apr 12, 2000 Issued
Array ( [id] => 1429580 [patent_doc_number] => 06515932 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Memory circuit' [patent_app_type] => B1 [patent_app_number] => 09/548121 [patent_app_country] => US [patent_app_date] => 2000-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4698 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515932.pdf [firstpage_image] =>[orig_patent_app_number] => 09548121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/548121
Memory circuit Apr 11, 2000 Issued
Array ( [id] => 4305387 [patent_doc_number] => 06236618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Centrally decoded divided wordline (DWL) memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/542033 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4834 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236618.pdf [firstpage_image] =>[orig_patent_app_number] => 542033 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542033
Centrally decoded divided wordline (DWL) memory architecture Apr 2, 2000 Issued
Array ( [id] => 4396850 [patent_doc_number] => 06262931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Semiconductor memory device having voltage down convertor reducing current consumption' [patent_app_type] => 1 [patent_app_number] => 9/539893 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 12536 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262931.pdf [firstpage_image] =>[orig_patent_app_number] => 539893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/539893
Semiconductor memory device having voltage down convertor reducing current consumption Mar 30, 2000 Issued
Array ( [id] => 1546838 [patent_doc_number] => 06373749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Channel-erase nonvolatile semiconductor memory device' [patent_app_type] => B1 [patent_app_number] => 09/536391 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 5989 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373749.pdf [firstpage_image] =>[orig_patent_app_number] => 09536391 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536391
Channel-erase nonvolatile semiconductor memory device Mar 27, 2000 Issued
Array ( [id] => 4346236 [patent_doc_number] => 06333876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/536697 [patent_app_country] => US [patent_app_date] => 2000-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7888 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333876.pdf [firstpage_image] =>[orig_patent_app_number] => 536697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/536697
Semiconductor memory device Mar 27, 2000 Issued
Array ( [id] => 1555120 [patent_doc_number] => 06400615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-04 [patent_title] => 'Voltage raising circuit for semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 09/531499 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3540 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400615.pdf [firstpage_image] =>[orig_patent_app_number] => 09531499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531499
Voltage raising circuit for semiconductor memory Mar 20, 2000 Issued
Array ( [id] => 4327381 [patent_doc_number] => 06243297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 9/527293 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7225 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243297.pdf [firstpage_image] =>[orig_patent_app_number] => 527293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527293
Semiconductor storage device Mar 16, 2000 Issued
Array ( [id] => 4272688 [patent_doc_number] => 06205056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Automated reference cell trimming verify' [patent_app_type] => 1 [patent_app_number] => 9/524897 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3741 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205056.pdf [firstpage_image] =>[orig_patent_app_number] => 524897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524897
Automated reference cell trimming verify Mar 13, 2000 Issued
Array ( [id] => 4272619 [patent_doc_number] => 06205051 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Stabilized magnetic memory cell' [patent_app_type] => 1 [patent_app_number] => 9/522269 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2567 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205051.pdf [firstpage_image] =>[orig_patent_app_number] => 522269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522269
Stabilized magnetic memory cell Mar 8, 2000 Issued
Array ( [id] => 4373912 [patent_doc_number] => 06256229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Apparatus and method for programming voltage protection in a non-volatile memory system' [patent_app_type] => 1 [patent_app_number] => 9/516532 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6818 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256229.pdf [firstpage_image] =>[orig_patent_app_number] => 516532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516532
Apparatus and method for programming voltage protection in a non-volatile memory system Feb 29, 2000 Issued
Array ( [id] => 4420038 [patent_doc_number] => 06266277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Apparatus and method for programming voltage protection in a non-volatile memory system' [patent_app_type] => 1 [patent_app_number] => 9/516550 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6794 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266277.pdf [firstpage_image] =>[orig_patent_app_number] => 516550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516550
Apparatus and method for programming voltage protection in a non-volatile memory system Feb 29, 2000 Issued
Array ( [id] => 1585342 [patent_doc_number] => 06424569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'User selectable cell programming' [patent_app_type] => B1 [patent_app_number] => 09/513027 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2417 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424569.pdf [firstpage_image] =>[orig_patent_app_number] => 09513027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513027
User selectable cell programming Feb 24, 2000 Issued
Array ( [id] => 1565242 [patent_doc_number] => 06363025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Power up initialization circuit responding to an input signal' [patent_app_type] => B1 [patent_app_number] => 09/511884 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363025.pdf [firstpage_image] =>[orig_patent_app_number] => 09511884 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511884
Power up initialization circuit responding to an input signal Feb 22, 2000 Issued
Array ( [id] => 1465212 [patent_doc_number] => 06351421 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Data output buffer' [patent_app_type] => B1 [patent_app_number] => 09/510021 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3292 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351421.pdf [firstpage_image] =>[orig_patent_app_number] => 09510021 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510021
Data output buffer Feb 21, 2000 Issued
Array ( [id] => 1565263 [patent_doc_number] => 06363029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions' [patent_app_type] => B1 [patent_app_number] => 09/506438 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 75 [patent_no_of_words] => 24783 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363029.pdf [firstpage_image] =>[orig_patent_app_number] => 09506438 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506438
Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions Feb 17, 2000 Issued
Array ( [id] => 4262815 [patent_doc_number] => 06222772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Methods of performing sector erase operations on non-volatile semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/506997 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3944 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222772.pdf [firstpage_image] =>[orig_patent_app_number] => 506997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506997
Methods of performing sector erase operations on non-volatile semiconductor memory devices Feb 17, 2000 Issued
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