
Gregory A. Anderson
Examiner (ID: 3781, Phone: (571)270-3083 , Office: P/3731 )
| Most Active Art Unit | 3773 |
| Art Unit(s) | 3700, 3773, 3731, 3771, 3709, 4138 |
| Total Applications | 754 |
| Issued Applications | 532 |
| Pending Applications | 44 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4250344
[patent_doc_number] => 06081443
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-27
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/222799
[patent_app_country] => US
[patent_app_date] => 1998-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 65
[patent_no_of_words] => 55066
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/081/06081443.pdf
[firstpage_image] =>[orig_patent_app_number] => 222799
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222799 | Semiconductor memory device | Dec 29, 1998 | Issued |
Array
(
[id] => 3964334
[patent_doc_number] => 05978299
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation'
[patent_app_type] => 1
[patent_app_number] => 9/222793
[patent_app_country] => US
[patent_app_date] => 1998-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 27
[patent_no_of_words] => 8974
[patent_no_of_claims] => 1
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[patent_words_short_claim] => 270
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/978/05978299.pdf
[firstpage_image] =>[orig_patent_app_number] => 222793
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/222793 | Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation | Dec 29, 1998 | Issued |
Array
(
[id] => 4250366
[patent_doc_number] => 06144582
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/220328
[patent_app_country] => US
[patent_app_date] => 1998-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5213
[patent_no_of_claims] => 27
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[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144582.pdf
[firstpage_image] =>[orig_patent_app_number] => 220328
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/220328 | Nonvolatile semiconductor memory device | Dec 23, 1998 | Issued |
| 09/219416 | SEMICONDUCTOR STORAGE DEVICE | Dec 22, 1998 | Abandoned |
Array
(
[id] => 4108792
[patent_doc_number] => 06049482
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 9/217015
[patent_app_country] => US
[patent_app_date] => 1998-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 7806
[patent_no_of_claims] => 20
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/049/06049482.pdf
[firstpage_image] =>[orig_patent_app_number] => 217015
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/217015 | Non-volatile semiconductor memory device | Dec 20, 1998 | Issued |
Array
(
[id] => 4171330
[patent_doc_number] => 06115282
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Dynamic memory'
[patent_app_type] => 1
[patent_app_number] => 9/215906
[patent_app_country] => US
[patent_app_date] => 1998-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 5889
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/115/06115282.pdf
[firstpage_image] =>[orig_patent_app_number] => 215906
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/215906 | Dynamic memory | Dec 17, 1998 | Issued |
Array
(
[id] => 4246096
[patent_doc_number] => 06075734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Integrated circuit memory device for storing a multi-bit data and a method for reading stored data in the same'
[patent_app_type] => 1
[patent_app_number] => 9/213616
[patent_app_country] => US
[patent_app_date] => 1998-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4242
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/075/06075734.pdf
[firstpage_image] =>[orig_patent_app_number] => 213616
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/213616 | Integrated circuit memory device for storing a multi-bit data and a method for reading stored data in the same | Dec 16, 1998 | Issued |
Array
(
[id] => 4309177
[patent_doc_number] => 06181612
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Semiconductor memory capable of burst operation'
[patent_app_type] => 1
[patent_app_number] => 9/213279
[patent_app_country] => US
[patent_app_date] => 1998-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 12669
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/181/06181612.pdf
[firstpage_image] =>[orig_patent_app_number] => 213279
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/213279 | Semiconductor memory capable of burst operation | Dec 16, 1998 | Issued |
Array
(
[id] => 4153132
[patent_doc_number] => 06061288
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-09
[patent_title] => 'Semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/210819
[patent_app_country] => US
[patent_app_date] => 1998-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8710
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/061/06061288.pdf
[firstpage_image] =>[orig_patent_app_number] => 210819
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/210819 | Semiconductor device | Dec 14, 1998 | Issued |
Array
(
[id] => 4251936
[patent_doc_number] => 06091652
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-18
[patent_title] => 'Testing semiconductor devices for data retention'
[patent_app_type] => 1
[patent_app_number] => 9/209907
[patent_app_country] => US
[patent_app_date] => 1998-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2321
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/091/06091652.pdf
[firstpage_image] =>[orig_patent_app_number] => 209907
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/209907 | Testing semiconductor devices for data retention | Dec 10, 1998 | Issued |
Array
(
[id] => 4144576
[patent_doc_number] => 06016265
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Fuse-latch circuit having high integration density'
[patent_app_type] => 1
[patent_app_number] => 9/209120
[patent_app_country] => US
[patent_app_date] => 1998-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3580
[patent_no_of_claims] => 13
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/016/06016265.pdf
[firstpage_image] =>[orig_patent_app_number] => 209120
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/209120 | Fuse-latch circuit having high integration density | Dec 9, 1998 | Issued |
Array
(
[id] => 4093431
[patent_doc_number] => 06055187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells'
[patent_app_type] => 1
[patent_app_number] => 9/209319
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/055/06055187.pdf
[firstpage_image] =>[orig_patent_app_number] => 209319
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/209319 | Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells | Dec 8, 1998 | Issued |
Array
(
[id] => 4148099
[patent_doc_number] => 06122216
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Single package dual memory device'
[patent_app_type] => 1
[patent_app_number] => 9/208306
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/122/06122216.pdf
[firstpage_image] =>[orig_patent_app_number] => 208306
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/208306 | Single package dual memory device | Dec 8, 1998 | Issued |
Array
(
[id] => 4170133
[patent_doc_number] => 06104642
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-15
[patent_title] => 'Method and apparatus for 1 of 4 register file design'
[patent_app_type] => 1
[patent_app_number] => 9/207806
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/104/06104642.pdf
[firstpage_image] =>[orig_patent_app_number] => 207806
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/207806 | Method and apparatus for 1 of 4 register file design | Dec 8, 1998 | Issued |
| 09/207287 | LOW VOLTAGE SINGLE CMOS ELECTRICALLY ERASABLE READ-ONLY MEMORY | Dec 7, 1998 | Abandoned |
Array
(
[id] => 4216914
[patent_doc_number] => 06078530
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Reference voltage generator for a ferroelectric material memory device'
[patent_app_type] => 1
[patent_app_number] => 9/206308
[patent_app_country] => US
[patent_app_date] => 1998-12-07
[patent_effective_date] => 0000-00-00
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/078/06078530.pdf
[firstpage_image] =>[orig_patent_app_number] => 206308
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206308 | Reference voltage generator for a ferroelectric material memory device | Dec 6, 1998 | Issued |
Array
(
[id] => 1465229
[patent_doc_number] => 06351427
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Stored write scheme for high speed/wide bandwidth memory devices'
[patent_app_type] => B1
[patent_app_number] => 09/207119
[patent_app_country] => US
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[pdf_file] => patents/06/351/06351427.pdf
[firstpage_image] =>[orig_patent_app_number] => 09207119
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/207119 | Stored write scheme for high speed/wide bandwidth memory devices | Dec 6, 1998 | Issued |
Array
(
[id] => 4230724
[patent_doc_number] => 06041009
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-21
[patent_title] => 'Apparatus for stabilizing an antifuse used for a memory device'
[patent_app_type] => 1
[patent_app_number] => 9/206318
[patent_app_country] => US
[patent_app_date] => 1998-12-07
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/041/06041009.pdf
[firstpage_image] =>[orig_patent_app_number] => 206318
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206318 | Apparatus for stabilizing an antifuse used for a memory device | Dec 6, 1998 | Issued |
Array
(
[id] => 4309281
[patent_doc_number] => 06181619
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Selective automatic precharge of dynamic random access memory banks'
[patent_app_type] => 1
[patent_app_number] => 9/205508
[patent_app_country] => US
[patent_app_date] => 1998-12-04
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/181/06181619.pdf
[firstpage_image] =>[orig_patent_app_number] => 205508
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205508 | Selective automatic precharge of dynamic random access memory banks | Dec 3, 1998 | Issued |
Array
(
[id] => 4110602
[patent_doc_number] => 06097658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'DRAM with reduced electric power consumption'
[patent_app_type] => 1
[patent_app_number] => 9/189148
[patent_app_country] => US
[patent_app_date] => 1998-11-10
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/097/06097658.pdf
[firstpage_image] =>[orig_patent_app_number] => 189148
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/189148 | DRAM with reduced electric power consumption | Nov 9, 1998 | Issued |