Search

Gregory Aaron Kessler

Examiner (ID: 14366, Phone: (571)270-7762 , Office: P/2196 )

Most Active Art Unit
2196
Art Unit(s)
2196, 2195, 2197
Total Applications
1021
Issued Applications
883
Pending Applications
58
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8260005 [patent_doc_number] => 08209518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Processing bypass directory tracking system and method' [patent_app_type] => utility [patent_app_number] => 13/073895 [patent_app_country] => US [patent_app_date] => 2011-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13073895 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/073895
Processing bypass directory tracking system and method Mar 27, 2011 Issued
Array ( [id] => 8001163 [patent_doc_number] => 08082429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Information processing apparatus and exception control circuit' [patent_app_type] => utility [patent_app_number] => 13/052281 [patent_app_country] => US [patent_app_date] => 2011-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5748 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082429.pdf [firstpage_image] =>[orig_patent_app_number] => 13052281 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/052281
Information processing apparatus and exception control circuit Mar 20, 2011 Issued
Array ( [id] => 6147351 [patent_doc_number] => 20110131394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'APPARATUS AND METHOD FOR USING BRANCH PREDICTION HEURISTICS FOR DETERMINATION OF TRACE FORMATION READINESS' [patent_app_type] => utility [patent_app_number] => 13/016144 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2524 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131394.pdf [firstpage_image] =>[orig_patent_app_number] => 13016144 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016144
Apparatus and method for using branch prediction heuristics for determination of trace formation readiness Jan 27, 2011 Issued
Array ( [id] => 7682588 [patent_doc_number] => 20100241823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'DATA PROCESSING DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/791322 [patent_app_country] => US [patent_app_date] => 2010-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 22135 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20100241823.pdf [firstpage_image] =>[orig_patent_app_number] => 12791322 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/791322
DATA PROCESSING DEVICE AND METHOD May 31, 2010 Abandoned
Array ( [id] => 6564278 [patent_doc_number] => 20100223448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Computer Configuration Virtual Topology Discovery and Instruction Therefore' [patent_app_type] => utility [patent_app_number] => 12/779232 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 18010 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20100223448.pdf [firstpage_image] =>[orig_patent_app_number] => 12779232 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/779232
Computer configuration virtual topology discovery and instruction therefore May 12, 2010 Issued
Array ( [id] => 4602829 [patent_doc_number] => 07979673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Method and apparatus for matrix decompositions in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/777193 [patent_app_country] => US [patent_app_date] => 2010-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 8332 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979673.pdf [firstpage_image] =>[orig_patent_app_number] => 12777193 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/777193
Method and apparatus for matrix decompositions in programmable logic devices May 9, 2010 Issued
Array ( [id] => 8033567 [patent_doc_number] => 08145879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Computer memory architecture for hybrid serial and parallel computing systems' [patent_app_type] => utility [patent_app_number] => 12/721252 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7662 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/145/08145879.pdf [firstpage_image] =>[orig_patent_app_number] => 12721252 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721252
Computer memory architecture for hybrid serial and parallel computing systems Mar 9, 2010 Issued
Array ( [id] => 6646656 [patent_doc_number] => 20100174883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'PROCESSOR ARCHITECTURES FOR ENHANCED COMPUTATIONAL CAPABILITY AND LOW LATENCY' [patent_app_type] => utility [patent_app_number] => 12/701090 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20100174883.pdf [firstpage_image] =>[orig_patent_app_number] => 12701090 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/701090
Processor architectures for enhanced computational capability and low latency Feb 4, 2010 Issued
Array ( [id] => 4532878 [patent_doc_number] => RE042466 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2011-06-14 [patent_title] => 'Branch predicting apparatus and branch predicting method' [patent_app_type] => reissue [patent_app_number] => 12/656111 [patent_app_country] => US [patent_app_date] => 2010-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 56 [patent_no_of_words] => 17128 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/042/RE042466.pdf [firstpage_image] =>[orig_patent_app_number] => 12656111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656111
Branch predicting apparatus and branch predicting method Jan 14, 2010 Issued
Array ( [id] => 4522339 [patent_doc_number] => 07917736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-29 [patent_title] => 'Latency tolerant pipeline synchronization' [patent_app_type] => utility [patent_app_number] => 12/614236 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4879 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917736.pdf [firstpage_image] =>[orig_patent_app_number] => 12614236 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/614236
Latency tolerant pipeline synchronization Nov 5, 2009 Issued
Array ( [id] => 4549311 [patent_doc_number] => 07925867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Pre-decode checking for pre-decoded instructions that cross cache line boundaries' [patent_app_type] => utility [patent_app_number] => 12/458512 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 36 [patent_no_of_words] => 16630 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/925/07925867.pdf [firstpage_image] =>[orig_patent_app_number] => 12458512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/458512
Pre-decode checking for pre-decoded instructions that cross cache line boundaries Jul 13, 2009 Issued
Array ( [id] => 6100432 [patent_doc_number] => 20110004743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'Pipe scheduling for pipelines based on destination register number' [patent_app_type] => utility [patent_app_number] => 12/458162 [patent_app_country] => US [patent_app_date] => 2009-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3971 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004743.pdf [firstpage_image] =>[orig_patent_app_number] => 12458162 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/458162
Pipe scheduling for pipelines based on destination register number Jun 30, 2009 Issued
Array ( [id] => 4447742 [patent_doc_number] => 07930686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Defining memory indifferent trace handles' [patent_app_type] => utility [patent_app_number] => 12/487906 [patent_app_country] => US [patent_app_date] => 2009-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3895 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930686.pdf [firstpage_image] =>[orig_patent_app_number] => 12487906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/487906
Defining memory indifferent trace handles Jun 18, 2009 Issued
Array ( [id] => 6554536 [patent_doc_number] => 20100205404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC MICROCODE-IMPLEMENTED INSTRUCTION STATE' [patent_app_type] => utility [patent_app_number] => 12/481487 [patent_app_country] => US [patent_app_date] => 2009-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12336 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205404.pdf [firstpage_image] =>[orig_patent_app_number] => 12481487 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/481487
Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state Jun 8, 2009 Issued
Array ( [id] => 7521024 [patent_doc_number] => 07975132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor' [patent_app_type] => utility [patent_app_number] => 12/481074 [patent_app_country] => US [patent_app_date] => 2009-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 13337 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975132.pdf [firstpage_image] =>[orig_patent_app_number] => 12481074 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/481074
Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor Jun 8, 2009 Issued
Array ( [id] => 6554485 [patent_doc_number] => 20100205401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'PIPELINED MICROPROCESSOR WITH FAST NON-SELECTIVE CORRECT CONDITIONAL BRANCH INSTRUCTION RESOLUTION' [patent_app_type] => utility [patent_app_number] => 12/481035 [patent_app_country] => US [patent_app_date] => 2009-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8033 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205401.pdf [firstpage_image] =>[orig_patent_app_number] => 12481035 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/481035
Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution Jun 8, 2009 Issued
Array ( [id] => 6554750 [patent_doc_number] => 20100205415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC SERIALIZING INSTRUCTION STATE' [patent_app_type] => utility [patent_app_number] => 12/481499 [patent_app_country] => US [patent_app_date] => 2009-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12310 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205415.pdf [firstpage_image] =>[orig_patent_app_number] => 12481499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/481499
Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state Jun 8, 2009 Issued
Array ( [id] => 6262674 [patent_doc_number] => 20100031004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'ARITHMETIC DEVICE' [patent_app_type] => utility [patent_app_number] => 12/480321 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 22476 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20100031004.pdf [firstpage_image] =>[orig_patent_app_number] => 12480321 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/480321
ARITHMETIC DEVICE Jun 7, 2009 Abandoned
Array ( [id] => 6643568 [patent_doc_number] => 20100312989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'Register renaming of a partially updated data granule' [patent_app_type] => utility [patent_app_number] => 12/457261 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4850 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0312/20100312989.pdf [firstpage_image] =>[orig_patent_app_number] => 12457261 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/457261
Register renaming of a partially updated data granule Jun 3, 2009 Issued
Array ( [id] => 5535265 [patent_doc_number] => 20090235053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'System and Method for Register Renaming' [patent_app_type] => utility [patent_app_number] => 12/472052 [patent_app_country] => US [patent_app_date] => 2009-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4434 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20090235053.pdf [firstpage_image] =>[orig_patent_app_number] => 12472052 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/472052
System and method for register renaming May 25, 2009 Issued
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