Gregory Aaron Kessler

Array ( [id] => 7601950 [patent_doc_number] => 07237094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Instruction group formation and mechanism for SMT dispatch' [patent_app_type] => utility [patent_app_number] => 10/965143 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5527 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237094.pdf [firstpage_image] =>[orig_patent_app_number] => 10965143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 623299 [patent_doc_number] => 07143271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Automatic register backup/restore system and method' [patent_app_type] => utility [patent_app_number] => 10/959778 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4850 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143271.pdf [firstpage_image] =>[orig_patent_app_number] => 10959778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7077296 [patent_doc_number] => 20050149772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Microprocessor for reducing leakage power and method thereof' [patent_app_type] => utility [patent_app_number] => 10/957617 [patent_app_country] => US [patent_app_date] => 2004-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2672 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149772.pdf [firstpage_image] =>[orig_patent_app_number] => 10957617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5867127 [patent_doc_number] => 20060101258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Microprocessor instructions for efficient bit stream extractions' [patent_app_type] => utility [patent_app_number] => 10/956490 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11898 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101258.pdf [firstpage_image] =>[orig_patent_app_number] => 10956490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5809372 [patent_doc_number] => 20060095728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method and apparatus to provide a source operand for an instruction in a processor' [patent_app_type] => utility [patent_app_number] => 10/953760 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5737 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095728.pdf [firstpage_image] =>[orig_patent_app_number] => 10953760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5809374 [patent_doc_number] => 20060095730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses' [patent_app_type] => utility [patent_app_number] => 10/955643 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7579 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095730.pdf [firstpage_image] =>[orig_patent_app_number] => 10955643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5132528 [patent_doc_number] => 20070208925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'Device And Method For Rendering Data' [patent_app_type] => utility [patent_app_number] => 10/573978 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20070208925.pdf [firstpage_image] =>[orig_patent_app_number] => 10573978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6972841 [patent_doc_number] => 20050038550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Program product and data processing system' [patent_app_type] => utility [patent_app_number] => 10/946746 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11629 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20050038550.pdf [firstpage_image] =>[orig_patent_app_number] => 10946746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 792689 [patent_doc_number] => 06986020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller' [patent_app_type] => utility [patent_app_number] => 10/946261 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6297 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/986/06986020.pdf [firstpage_image] =>[orig_patent_app_number] => 10946261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6973816 [patent_doc_number] => 20050038977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Processor with instructions that operate on different data types stored in the same single logical register file' [patent_app_type] => utility [patent_app_number] => 10/940268 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 32274 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20050038977.pdf [firstpage_image] =>[orig_patent_app_number] => 10940268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7532562 [patent_doc_number] => 07844796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Data processing device and method' [patent_app_type] => utility [patent_app_number] => 10/570173 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 54 [patent_no_of_words] => 22037 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844796.pdf [firstpage_image] =>[orig_patent_app_number] => 10570173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7742315 [patent_doc_number] => 08106679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Data processing system' [patent_app_type] => utility [patent_app_number] => 10/568666 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 13722 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/106/08106679.pdf [firstpage_image] =>[orig_patent_app_number] => 10568666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5248899 [patent_doc_number] => 20070245133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Method and Device for Switching Between at Least Two Operating Modes of a Processor Unit' [patent_app_type] => utility [patent_app_number] => 10/577009 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4656 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20070245133.pdf [firstpage_image] =>[orig_patent_app_number] => 10577009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4498812 [patent_doc_number] => 07886129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Configurable co-processor interface' [patent_app_type] => utility [patent_app_number] => 10/923584 [patent_app_country] => US [patent_app_date] => 2004-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 12339 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886129.pdf [firstpage_image] =>[orig_patent_app_number] => 10923584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 107696 [patent_doc_number] => 07725681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Parallel processing array' [patent_app_type] => utility [patent_app_number] => 10/568013 [patent_app_country] => US [patent_app_date] => 2004-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2665 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725681.pdf [firstpage_image] =>[orig_patent_app_number] => 10568013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 188583 [patent_doc_number] => 07647480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Handling of conditional instructions in a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/632698 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6145 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647480.pdf [firstpage_image] =>[orig_patent_app_number] => 11632698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 839879 [patent_doc_number] => 07395409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Split embedded DRAM processor' [patent_app_type] => utility [patent_app_number] => 10/884132 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 15341 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395409.pdf [firstpage_image] =>[orig_patent_app_number] => 10884132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7359237 [patent_doc_number] => 20040250150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Devices, systems and methods for mode driven stops notice' [patent_app_type] => new [patent_app_number] => 10/882476 [patent_app_country] => US [patent_app_date] => 2004-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 37601 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20040250150.pdf [firstpage_image] =>[orig_patent_app_number] => 10882476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5086972 [patent_doc_number] => 20070277023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Method For Switching Over Between At Least Two Operating Modes Of A Processor Unit, As Well Corresponding Processor Unit' [patent_app_type] => utility [patent_app_number] => 10/560962 [patent_app_country] => US [patent_app_date] => 2004-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4324 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20070277023.pdf [firstpage_image] =>[orig_patent_app_number] => 10560962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7321262 [patent_doc_number] => 20040225871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Branch control memory' [patent_app_type] => new [patent_app_number] => 10/869760 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18318 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225871.pdf [firstpage_image] =>[orig_patent_app_number] => 10869760 [rel_patent_id] =>[rel_patent_doc_number] =>)