Search

Gregory Aaron Kessler

Examiner (ID: 14366, Phone: (571)270-7762 , Office: P/2196 )

Most Active Art Unit
2196
Art Unit(s)
2196, 2195, 2197
Total Applications
1021
Issued Applications
883
Pending Applications
58
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7449099 [patent_doc_number] => 20040268087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method and apparatus for NOP folding' [patent_app_type] => new [patent_app_number] => 10/606511 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4943 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268087.pdf [firstpage_image] =>[orig_patent_app_number] => 10606511 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/606511
Method and apparatus for NOP folding Jun 24, 2003 Issued
Array ( [id] => 766017 [patent_doc_number] => 07013383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Apparatus and method for managing a processor pipeline in response to exceptions' [patent_app_type] => utility [patent_app_number] => 10/602931 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6733 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/013/07013383.pdf [firstpage_image] =>[orig_patent_app_number] => 10602931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602931
Apparatus and method for managing a processor pipeline in response to exceptions Jun 23, 2003 Issued
Array ( [id] => 757711 [patent_doc_number] => 07024544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Apparatus and method for accessing registers in a processor' [patent_app_type] => utility [patent_app_number] => 10/602813 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5101 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024544.pdf [firstpage_image] =>[orig_patent_app_number] => 10602813 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602813
Apparatus and method for accessing registers in a processor Jun 23, 2003 Issued
Array ( [id] => 7262099 [patent_doc_number] => 20040260914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Data packet arithmetic logic devices and methods' [patent_app_type] => new [patent_app_number] => 10/602349 [patent_app_country] => US [patent_app_date] => 2003-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8386 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20040260914.pdf [firstpage_image] =>[orig_patent_app_number] => 10602349 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602349
Data packet arithmetic logic devices and methods Jun 22, 2003 Issued
Array ( [id] => 731310 [patent_doc_number] => 07047401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Handling interrupts during multiple access program instructions' [patent_app_type] => utility [patent_app_number] => 10/461335 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4397 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047401.pdf [firstpage_image] =>[orig_patent_app_number] => 10461335 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/461335
Handling interrupts during multiple access program instructions Jun 15, 2003 Issued
Array ( [id] => 633371 [patent_doc_number] => 07134001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-07 [patent_title] => 'Pipeline replay support for unaligned memory operations' [patent_app_type] => utility [patent_app_number] => 10/463223 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8948 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/134/07134001.pdf [firstpage_image] =>[orig_patent_app_number] => 10463223 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463223
Pipeline replay support for unaligned memory operations Jun 15, 2003 Issued
Array ( [id] => 7611330 [patent_doc_number] => 06904512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Data flow processor' [patent_app_type] => utility [patent_app_number] => 10/461847 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5902 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904512.pdf [firstpage_image] =>[orig_patent_app_number] => 10461847 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/461847
Data flow processor Jun 12, 2003 Issued
Array ( [id] => 6810485 [patent_doc_number] => 20030200424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Master-slave latch circuit for multithreaded processing' [patent_app_type] => new [patent_app_number] => 10/459646 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 6914 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200424.pdf [firstpage_image] =>[orig_patent_app_number] => 10459646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/459646
Master-slave latch circuit for multithreaded processing Jun 9, 2003 Abandoned
Array ( [id] => 1068347 [patent_doc_number] => 06848041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Methods and apparatus for scalable instruction set architecture with dynamic compact instructions' [patent_app_type] => utility [patent_app_number] => 10/424961 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 9458 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/848/06848041.pdf [firstpage_image] =>[orig_patent_app_number] => 10424961 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/424961
Methods and apparatus for scalable instruction set architecture with dynamic compact instructions Apr 27, 2003 Issued
Array ( [id] => 7206781 [patent_doc_number] => 20050166034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Processing method and apparatus for implementing systolic arrays' [patent_app_type] => utility [patent_app_number] => 10/511504 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2188 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20050166034.pdf [firstpage_image] =>[orig_patent_app_number] => 10511504 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/511504
Processing method and apparatus for implementing systolic arrays Mar 31, 2003 Issued
Array ( [id] => 662976 [patent_doc_number] => 07107432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'VLIW processor with data spilling means' [patent_app_type] => utility [patent_app_number] => 10/511208 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1706 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/107/07107432.pdf [firstpage_image] =>[orig_patent_app_number] => 10511208 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/511208
VLIW processor with data spilling means Mar 31, 2003 Issued
Array ( [id] => 458022 [patent_doc_number] => 07249244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Data processing system' [patent_app_type] => utility [patent_app_number] => 10/510587 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5307 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/249/07249244.pdf [firstpage_image] =>[orig_patent_app_number] => 10510587 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/510587
Data processing system Mar 30, 2003 Issued
Array ( [id] => 7233196 [patent_doc_number] => 20050262332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Method and system for branch target prediction using path information' [patent_app_type] => utility [patent_app_number] => 10/404384 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10642 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20050262332.pdf [firstpage_image] =>[orig_patent_app_number] => 10404384 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/404384
Method and system for branch target prediction using path information Mar 30, 2003 Abandoned
Array ( [id] => 534703 [patent_doc_number] => 07194607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method and apparatus for command translation and enforcement of ordering of commands' [patent_app_type] => utility [patent_app_number] => 10/404888 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194607.pdf [firstpage_image] =>[orig_patent_app_number] => 10404888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/404888
Method and apparatus for command translation and enforcement of ordering of commands Mar 30, 2003 Issued
Array ( [id] => 6712505 [patent_doc_number] => 20030172254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Instructions for manipulating vectored data' [patent_app_type] => new [patent_app_number] => 10/358757 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 15092 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20030172254.pdf [firstpage_image] =>[orig_patent_app_number] => 10358757 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358757
Instructions for manipulating vectored data Feb 3, 2003 Abandoned
Array ( [id] => 6685040 [patent_doc_number] => 20030120904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Decompression bit processing with a general purpose alignment tool' [patent_app_type] => new [patent_app_number] => 10/356437 [patent_app_country] => US [patent_app_date] => 2003-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3918 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20030120904.pdf [firstpage_image] =>[orig_patent_app_number] => 10356437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356437
Decompression bit processing with a general purpose alignment tool Jan 30, 2003 Issued
Array ( [id] => 1177935 [patent_doc_number] => 06760866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Process of operating a processor with domains and clocks' [patent_app_type] => B2 [patent_app_number] => 10/336986 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 47 [patent_no_of_words] => 37409 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760866.pdf [firstpage_image] =>[orig_patent_app_number] => 10336986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336986
Process of operating a processor with domains and clocks Jan 5, 2003 Issued
Array ( [id] => 7293441 [patent_doc_number] => 20040111587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Apparatus and method for matrix data processing' [patent_app_type] => new [patent_app_number] => 10/315700 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8088 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20040111587.pdf [firstpage_image] =>[orig_patent_app_number] => 10315700 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/315700
Apparatus and method for matrix data processing Dec 8, 2002 Issued
Array ( [id] => 6698173 [patent_doc_number] => 20030110367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'External microcode' [patent_app_type] => new [patent_app_number] => 10/304199 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3072 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110367.pdf [firstpage_image] =>[orig_patent_app_number] => 10304199 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304199
External microcode Nov 25, 2002 Abandoned
Array ( [id] => 945813 [patent_doc_number] => 06968444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Microprocessor employing a fixed position dispatch unit' [patent_app_type] => utility [patent_app_number] => 10/287301 [patent_app_country] => US [patent_app_date] => 2002-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4461 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/968/06968444.pdf [firstpage_image] =>[orig_patent_app_number] => 10287301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287301
Microprocessor employing a fixed position dispatch unit Nov 3, 2002 Issued
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