Search

Gregory C. Issing

Examiner (ID: 4055, Phone: (571)272-6973 , Office: P/3646 )

Most Active Art Unit
2202
Art Unit(s)
2202, 3646, 3662, 3642
Total Applications
2605
Issued Applications
1869
Pending Applications
137
Abandoned Applications
598

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20388439 [patent_doc_number] => 12488167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Method and system for forward synthesis of digital predistortion nonlinear model derived from circuit description [patent_app_type] => utility [patent_app_number] => 19/223504 [patent_app_country] => US [patent_app_date] => 2025-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2375 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 753 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19223504 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/223504
Method and system for forward synthesis of digital predistortion nonlinear model derived from circuit description May 29, 2025 Issued
Array ( [id] => 19617853 [patent_doc_number] => 20240403533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => DESIGN AUTOMATION METHODS FOR 3D INTEGRATED CIRCUITS AND DEVICES [patent_app_type] => utility [patent_app_number] => 18/800058 [patent_app_country] => US [patent_app_date] => 2024-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18800058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/800058
Automation methods for 3D integrated circuits and devices Aug 9, 2024 Issued
Array ( [id] => 19499492 [patent_doc_number] => 20240338510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => TEST PATTERN GENERATION SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/745854 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745854
TEST PATTERN GENERATION SYSTEMS AND METHODS Jun 16, 2024 Pending
Array ( [id] => 19647121 [patent_doc_number] => 20240421641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => Systems And Methods For Wireless Power And Data Transfer Utilizing Multiple Antenna Receivers [patent_app_type] => utility [patent_app_number] => 18/744236 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744236
Systems and methods for wireless power and data transfer utilizing multiple antenna receivers Jun 13, 2024 Issued
Array ( [id] => 19482521 [patent_doc_number] => 20240330563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS [patent_app_type] => utility [patent_app_number] => 18/737156 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737156 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/737156
SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS Jun 6, 2024 Pending
Array ( [id] => 19435020 [patent_doc_number] => 20240303518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => COMBINED CLASSICAL/QUANTUM PREDICTOR EVALUATION WITH MODEL ACCURACY ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 18/668666 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668666 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668666
Combined classical/quantum predictor evaluation with model accuracy adjustment May 19, 2024 Issued
Array ( [id] => 19956660 [patent_doc_number] => 12327075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => System and method for clock distribution in a digital circuit [patent_app_type] => utility [patent_app_number] => 18/652787 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 29 [patent_no_of_words] => 5643 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652787 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652787
System and method for clock distribution in a digital circuit Apr 30, 2024 Issued
Array ( [id] => 19363154 [patent_doc_number] => 20240265188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/641386 [patent_app_country] => US [patent_app_date] => 2024-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/641386
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Apr 20, 2024 Pending
Array ( [id] => 19286512 [patent_doc_number] => 20240222992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => METHOD AND DEVICE FOR CONTROLLING THE LEVEL OF CHARGE OF A TRACTION BATTERY OF AN ELECTRIC VEHICLE [patent_app_type] => utility [patent_app_number] => 18/605421 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/605421
METHOD AND DEVICE FOR CONTROLLING THE LEVEL OF CHARGE OF A TRACTION BATTERY OF AN ELECTRIC VEHICLE Mar 13, 2024 Pending
Array ( [id] => 19236148 [patent_doc_number] => 20240193343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/587437 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587437
SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM Feb 25, 2024 Pending
Array ( [id] => 20457453 [patent_doc_number] => 12520525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Method and apparatus improving gate oxide reliability by controlling accumulated charge [patent_app_type] => utility [patent_app_number] => 18/439664 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 23919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439664
Method and apparatus improving gate oxide reliability by controlling accumulated charge Feb 11, 2024 Issued
Array ( [id] => 19925091 [patent_doc_number] => 12299375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Semiconductor process technology assessment [patent_app_type] => utility [patent_app_number] => 18/434345 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/434345
Semiconductor process technology assessment Feb 5, 2024 Issued
Array ( [id] => 19334631 [patent_doc_number] => 20240249061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => METHOD FOR INTEGRATED CIRCUIT DESIGN USING PIN DIRECTION OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/421808 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421808 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421808
METHOD FOR INTEGRATED CIRCUIT DESIGN USING PIN DIRECTION OPTIMIZATION Jan 23, 2024 Abandoned
Array ( [id] => 20274380 [patent_doc_number] => 12444163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Apparatus and methods for converting lineless tables into lined tables using generative adversarial networks [patent_app_type] => utility [patent_app_number] => 18/419946 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 724 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419946
Apparatus and methods for converting lineless tables into lined tables using generative adversarial networks Jan 22, 2024 Issued
Array ( [id] => 19144951 [patent_doc_number] => 20240143887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => METHOD AND SYSTEM FOR REDUCING LAYOUT DISTORTION DUE TO EXPOSURE NON-UNIFORMITY [patent_app_type] => utility [patent_app_number] => 18/404892 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404892 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404892
METHOD AND SYSTEM FOR REDUCING LAYOUT DISTORTION DUE TO EXPOSURE NON-UNIFORMITY Jan 4, 2024 Pending
Array ( [id] => 19857327 [patent_doc_number] => 12260165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture [patent_app_type] => utility [patent_app_number] => 18/378384 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10404 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378384 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378384
Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture Oct 9, 2023 Issued
Array ( [id] => 18864575 [patent_doc_number] => 20230419012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SYSTEMS AND METHODS FOR ELIMINATING ELECTROMIGRATION AND SELF-HEAT VIOLATIONS IN A MASK LAYOUT BLOCK [patent_app_type] => utility [patent_app_number] => 18/368038 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368038 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/368038
SYSTEMS AND METHODS FOR ELIMINATING ELECTROMIGRATION AND SELF-HEAT VIOLATIONS IN A MASK LAYOUT BLOCK Sep 13, 2023 Pending
Array ( [id] => 20331809 [patent_doc_number] => 12462086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Integrated circuit having hybrid sheet structure [patent_app_type] => utility [patent_app_number] => 18/448136 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448136
Integrated circuit having hybrid sheet structure Aug 9, 2023 Issued
Array ( [id] => 18811176 [patent_doc_number] => 20230385512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS [patent_app_type] => utility [patent_app_number] => 18/447964 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447964
METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS Aug 9, 2023 Pending
Array ( [id] => 19950317 [patent_doc_number] => 12321682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Post-routing congestion optimization [patent_app_type] => utility [patent_app_number] => 18/447567 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447567
Post-routing congestion optimization Aug 9, 2023 Issued
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