Search

Gregory C. Issing

Examiner (ID: 4055, Phone: (571)272-6973 , Office: P/3646 )

Most Active Art Unit
2202
Art Unit(s)
2202, 3646, 3662, 3642
Total Applications
2605
Issued Applications
1869
Pending Applications
137
Abandoned Applications
598

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18072969 [patent_doc_number] => 11531803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-20 [patent_title] => IPBA-driven full-depth EPBA of operational timing for circuit design [patent_app_type] => utility [patent_app_number] => 17/232616 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 14022 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232616 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232616
IPBA-driven full-depth EPBA of operational timing for circuit design Apr 15, 2021 Issued
Array ( [id] => 18248325 [patent_doc_number] => 11604915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Semiconductor process technology assessment [patent_app_type] => utility [patent_app_number] => 17/231194 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231194
Semiconductor process technology assessment Apr 14, 2021 Issued
Array ( [id] => 18527951 [patent_doc_number] => 11714945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Method for automated standard cell design [patent_app_type] => utility [patent_app_number] => 17/219539 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 54 [patent_no_of_words] => 15592 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219539
Method for automated standard cell design Mar 30, 2021 Issued
Array ( [id] => 18463404 [patent_doc_number] => 11687694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-27 [patent_title] => Method, product, and system for automated, guided, and region-based layer density balancing [patent_app_type] => utility [patent_app_number] => 17/219675 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/219675
Method, product, and system for automated, guided, and region-based layer density balancing Mar 30, 2021 Issued
Array ( [id] => 18204401 [patent_doc_number] => 11586796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-21 [patent_title] => Keep-through regions for handling end-of-line rules in routing [patent_app_type] => utility [patent_app_number] => 17/215448 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 6570 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215448
Keep-through regions for handling end-of-line rules in routing Mar 28, 2021 Issued
Array ( [id] => 16967132 [patent_doc_number] => 20210218631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SYSTEM FOR IMPLEMENTING A DATA LINK LAYER PROTOCOL IN A COMPUTE HOST [patent_app_type] => utility [patent_app_number] => 17/212975 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212975 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212975
SYSTEM FOR IMPLEMENTING A DATA LINK LAYER PROTOCOL IN A COMPUTE HOST Mar 24, 2021 Abandoned
Array ( [id] => 18934354 [patent_doc_number] => 11886788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Duplicate circuit section identification and processing for optical proximity correction (OPC) processes in electronic design automation (EDA) applications [patent_app_type] => utility [patent_app_number] => 17/212074 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212074
Duplicate circuit section identification and processing for optical proximity correction (OPC) processes in electronic design automation (EDA) applications Mar 24, 2021 Issued
Array ( [id] => 16967117 [patent_doc_number] => 20210218616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SYSTEM FOR HOSTING DATA LINK LAYER AGENT, PROTOCOL, AND MANAGEMENT FUNCTIONS [patent_app_type] => utility [patent_app_number] => 17/212969 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12864 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212969
SYSTEM FOR HOSTING DATA LINK LAYER AGENT, PROTOCOL, AND MANAGEMENT FUNCTIONS Mar 24, 2021 Abandoned
Array ( [id] => 17131437 [patent_doc_number] => 20210306206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SYSTEM FOR IMPLEMENTING A DATA PROTOCOL ENABLED APPLICATION [patent_app_type] => utility [patent_app_number] => 17/212981 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212981
SYSTEM FOR IMPLEMENTING A DATA PROTOCOL ENABLED APPLICATION Mar 24, 2021 Abandoned
Array ( [id] => 19044987 [patent_doc_number] => 11934094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Mask fingerprint using mask sensitive circuit [patent_app_type] => utility [patent_app_number] => 17/301032 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8039 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301032
Mask fingerprint using mask sensitive circuit Mar 22, 2021 Issued
Array ( [id] => 19399829 [patent_doc_number] => 12074217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction [patent_app_type] => utility [patent_app_number] => 17/206436 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 28751 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/206436
Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction Mar 18, 2021 Issued
Array ( [id] => 16935040 [patent_doc_number] => 20210200929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SYSTEM FOR DESIGNING A SEMICONDUCTOR DEVICE, DEVICE MADE, AND METHOD OF USING THE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/200366 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200366
System for designing a semiconductor device, device made, and method of using the system Mar 11, 2021 Issued
Array ( [id] => 18262341 [patent_doc_number] => 11610043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Machine learning based model builder and its applications for pattern transferring in semiconductor manufacturing [patent_app_type] => utility [patent_app_number] => 17/193625 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193625
Machine learning based model builder and its applications for pattern transferring in semiconductor manufacturing Mar 4, 2021 Issued
Array ( [id] => 18352403 [patent_doc_number] => 20230140514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => METHOD AND SYSTEM FOR ALLOCATING CHARGING RESOURCES TO A PLURALITY OF CHARGING STATIONS [patent_app_type] => utility [patent_app_number] => 17/906020 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17906020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/906020
METHOD AND SYSTEM FOR ALLOCATING CHARGING RESOURCES TO A PLURALITY OF CHARGING STATIONS Mar 3, 2021 Abandoned
Array ( [id] => 17824828 [patent_doc_number] => 11429776 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-30 [patent_title] => Fault rules files for testing an IC chip [patent_app_type] => utility [patent_app_number] => 17/181470 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11672 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181470
Fault rules files for testing an IC chip Feb 21, 2021 Issued
Array ( [id] => 17879454 [patent_doc_number] => 11451490 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => VLSI layouts of fully connected generalized and pyramid networks with locality exploitation [patent_app_type] => utility [patent_app_number] => 17/167082 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 51 [patent_no_of_words] => 37457 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167082 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167082
VLSI layouts of fully connected generalized and pyramid networks with locality exploitation Feb 3, 2021 Issued
Array ( [id] => 18356348 [patent_doc_number] => 11644746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-09 [patent_title] => Inverse etch model for mask synthesis [patent_app_type] => utility [patent_app_number] => 17/161345 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161345
Inverse etch model for mask synthesis Jan 27, 2021 Issued
Array ( [id] => 19280919 [patent_doc_number] => 20240217393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => BATTERY VOLTAGE EQUALIZATION DEVICE [patent_app_type] => utility [patent_app_number] => 17/907258 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6610 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17907258 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/907258
BATTERY VOLTAGE EQUALIZATION DEVICE Jan 26, 2021 Pending
Array ( [id] => 18155143 [patent_doc_number] => 11568123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Method for determining an etch profile of a layer of a wafer for a simulation system [patent_app_type] => utility [patent_app_number] => 17/157642 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 22537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157642
Method for determining an etch profile of a layer of a wafer for a simulation system Jan 24, 2021 Issued
Array ( [id] => 18155139 [patent_doc_number] => 11568119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Cell layout of semiconductor device [patent_app_type] => utility [patent_app_number] => 17/151189 [patent_app_country] => US [patent_app_date] => 2021-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17151189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/151189
Cell layout of semiconductor device Jan 16, 2021 Issued
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