Search

Gregory C. Issing

Examiner (ID: 4055, Phone: (571)272-6973 , Office: P/3646 )

Most Active Art Unit
2202
Art Unit(s)
2202, 3646, 3662, 3642
Total Applications
2605
Issued Applications
1869
Pending Applications
137
Abandoned Applications
598

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18788241 [patent_doc_number] => 20230376672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => INTEGRATED CIRCUIT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/362946 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362946
Integrated circuit structure Jul 30, 2023 Issued
Array ( [id] => 18810356 [patent_doc_number] => 20230384691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => OPTICAL PROXIMITY CORRECTION AND PHOTOMASKS [patent_app_type] => utility [patent_app_number] => 18/361879 [patent_app_country] => US [patent_app_date] => 2023-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361879
Optical proximity correction and photomasks Jul 29, 2023 Issued
Array ( [id] => 18904970 [patent_doc_number] => 20240020455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SOFTWARE-DEFINED WAFER-LEVEL SWITCHING SYSTEM DESIGN METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/351464 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351464
Software-defined wafer-level switching system design method and apparatus Jul 11, 2023 Issued
Array ( [id] => 18727476 [patent_doc_number] => 20230341765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => METHOD AND SYSTEM FOR LAYOUT ENHANCEMENT BASED ON INTER-CELL CORRELATION [patent_app_type] => utility [patent_app_number] => 18/344844 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344844
METHOD AND SYSTEM FOR LAYOUT ENHANCEMENT BASED ON INTER-CELL CORRELATION Jun 28, 2023 Pending
Array ( [id] => 18713397 [patent_doc_number] => 20230336033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => TWO-SIDED INDUCTIVE CHARGING COIL [patent_app_type] => utility [patent_app_number] => 18/213656 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213656
Two-sided inductive charging coil Jun 22, 2023 Issued
Array ( [id] => 20304425 [patent_doc_number] => 12450418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Semiconductor layout in FinFET technologies [patent_app_type] => utility [patent_app_number] => 18/337781 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337781 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337781
Semiconductor layout in FinFET technologies Jun 19, 2023 Issued
Array ( [id] => 18695154 [patent_doc_number] => 20230325574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => Method for Automated Standard Cell Design [patent_app_type] => utility [patent_app_number] => 18/333159 [patent_app_country] => US [patent_app_date] => 2023-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333159
Method for Automated Standard Cell Design Jun 11, 2023 Pending
Array ( [id] => 18657059 [patent_doc_number] => 20230302962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SYSTEM AND METHOD FOR DESIGNING AND CONTROLLING A DUAL ENERGY STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 18/313949 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313949 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313949
System and method for designing and controlling a dual energy storage system May 7, 2023 Issued
Array ( [id] => 20055797 [patent_doc_number] => 20250194019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => SYSTEMS AND METHODS FOR AUTOMATED DEGASSING DURING THE MANUFACTURING OF A HIGH SPEED DESIGN [patent_app_type] => utility [patent_app_number] => 18/307193 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307193 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307193
SYSTEMS AND METHODS FOR AUTOMATED DEGASSING DURING THE MANUFACTURING OF A HIGH SPEED DESIGN Apr 25, 2023 Pending
Array ( [id] => 18713377 [patent_doc_number] => 20230336013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => ADAPTING A BATTERY CHARGING PROFILE BASED ON NORMAL OPERATION OF A BATTERY-POWERED DEVICE [patent_app_type] => utility [patent_app_number] => 18/295530 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295530
ADAPTING A BATTERY CHARGING PROFILE BASED ON NORMAL OPERATION OF A BATTERY-POWERED DEVICE Apr 3, 2023 Pending
Array ( [id] => 18651914 [patent_doc_number] => 20230297750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => VARIATION-AWARE ANALOG CIRCUIT SIZING WITH CLASSIFIER CHAINS [patent_app_type] => utility [patent_app_number] => 18/185042 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18185042 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/185042
VARIATION-AWARE ANALOG CIRCUIT SIZING WITH CLASSIFIER CHAINS Mar 15, 2023 Pending
Array ( [id] => 18471688 [patent_doc_number] => 20230205974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => Semiconductor Process Technology Assessment [patent_app_type] => utility [patent_app_number] => 18/176701 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176701
Semiconductor process technology assessment Feb 28, 2023 Issued
Array ( [id] => 19406013 [patent_doc_number] => 20240289524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => VARIATION AWARE ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS [patent_app_type] => utility [patent_app_number] => 18/113582 [patent_app_country] => US [patent_app_date] => 2023-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18113582 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/113582
VARIATION AWARE ADJUSTMENTS TO SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS Feb 22, 2023 Pending
Array ( [id] => 18660170 [patent_doc_number] => 20230306177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => USING TOPOLOGICAL AND GEOMETRIC ROUTERS TO PRODUCE CURVILINEAR ROUTES [patent_app_type] => utility [patent_app_number] => 18/110344 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110344
USING TOPOLOGICAL AND GEOMETRIC ROUTERS TO PRODUCE CURVILINEAR ROUTES Feb 14, 2023 Pending
Array ( [id] => 18599266 [patent_doc_number] => 20230274066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => CONCURRENTLY ROUTING MULTIPLE PARTITIONS OF AN INTEGRATED CIRCUIT DESIGN [patent_app_type] => utility [patent_app_number] => 18/110346 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110346 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110346
CONCURRENTLY ROUTING MULTIPLE PARTITIONS OF AN INTEGRATED CIRCUIT DESIGN Feb 14, 2023 Pending
Array ( [id] => 19524451 [patent_doc_number] => 12126195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Battery life of battery powered wireless devices [patent_app_type] => utility [patent_app_number] => 18/109378 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18109378 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/109378
Battery life of battery powered wireless devices Feb 13, 2023 Issued
Array ( [id] => 18651920 [patent_doc_number] => 20230297756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => INTEGRATED CIRCUIT INTERCONNECT SHAPE OPTIMIZER [patent_app_type] => utility [patent_app_number] => 18/105737 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105737 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105737
INTEGRATED CIRCUIT INTERCONNECT SHAPE OPTIMIZER Feb 2, 2023 Pending
Array ( [id] => 19369162 [patent_doc_number] => 12061241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Rechargeable battery short circuit early detection device and rechargeable battery short circuit early detection method [patent_app_type] => utility [patent_app_number] => 18/104430 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8340 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104430 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104430
Rechargeable battery short circuit early detection device and rechargeable battery short circuit early detection method Jan 31, 2023 Issued
Array ( [id] => 18881703 [patent_doc_number] => 20240005072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD AND APPARATUS FOR CHECKING DATA PROCESSING CIRCUIT, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/162657 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162657
METHOD AND APPARATUS FOR CHECKING DATA PROCESSING CIRCUIT, AND ELECTRONIC DEVICE Jan 30, 2023 Pending
Array ( [id] => 19078520 [patent_doc_number] => 11947888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Semiconductor processing tools with improved performance by use of hybrid learning models [patent_app_type] => utility [patent_app_number] => 18/099130 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6137 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099130
Semiconductor processing tools with improved performance by use of hybrid learning models Jan 18, 2023 Issued
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