Search

Gregory C. Issing

Examiner (ID: 4055, Phone: (571)272-6973 , Office: P/3646 )

Most Active Art Unit
2202
Art Unit(s)
2202, 3646, 3662, 3642
Total Applications
2605
Issued Applications
1869
Pending Applications
137
Abandoned Applications
598

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18934355 [patent_doc_number] => 11886789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-30 [patent_title] => Block design containers for circuit design [patent_app_type] => utility [patent_app_number] => 17/369192 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 16531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369192
Block design containers for circuit design Jul 6, 2021 Issued
Array ( [id] => 19045652 [patent_doc_number] => 11934764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Routing and manufacturing with a minimum area metal structure [patent_app_type] => utility [patent_app_number] => 17/362662 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 8706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362662
Routing and manufacturing with a minimum area metal structure Jun 28, 2021 Issued
Array ( [id] => 18644918 [patent_doc_number] => 11768990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-26 [patent_title] => Interconnect flow graph for integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/305043 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305043 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305043
Interconnect flow graph for integrated circuit design Jun 28, 2021 Issued
Array ( [id] => 19427100 [patent_doc_number] => 12086522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Method of generating netlist including proximity-effect-inducer (PEI) parameters [patent_app_type] => utility [patent_app_number] => 17/353991 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 15236 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353991
Method of generating netlist including proximity-effect-inducer (PEI) parameters Jun 21, 2021 Issued
Array ( [id] => 19015340 [patent_doc_number] => 11922275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => System and method for determining a perturbation energy of a quantum state of a many-body system [patent_app_type] => utility [patent_app_number] => 17/351873 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351873
System and method for determining a perturbation energy of a quantum state of a many-body system Jun 17, 2021 Issued
Array ( [id] => 18890979 [patent_doc_number] => 11869756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Virtual metrology enhanced plasma process optimization method [patent_app_type] => utility [patent_app_number] => 17/350439 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350439
Virtual metrology enhanced plasma process optimization method Jun 16, 2021 Issued
Array ( [id] => 17114363 [patent_doc_number] => 20210294960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => SYSTEMS AND METHODS FOR INTELLIGENTLY BUFFER TRACKING FOR OPTIMIZED DATAFLOW WITHIN AN INTEGRATED CIRCUIT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/339291 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/339291
Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture Jun 3, 2021 Issued
Array ( [id] => 17261336 [patent_doc_number] => 20210374321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => SYSTEM AND METHOD FOR PROVIDING ENHANCED NET PRUNING [patent_app_type] => utility [patent_app_number] => 17/334495 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334495
System and method for providing enhanced net pruning May 27, 2021 Issued
Array ( [id] => 18038736 [patent_doc_number] => 20220382952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => OBSCURED METAL STACK DEFINITION TUNING FOR ELECTRONIC DESIGN AUTOMATION (EDA) APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/329614 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/329614
Obscured metal stack definition tuning for electronic design automation (EDA) applications May 24, 2021 Issued
Array ( [id] => 18577955 [patent_doc_number] => 11734488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => System and method to process a virtual partition cell injected into a hierarchical integrated circuit design [patent_app_type] => utility [patent_app_number] => 17/330018 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8293 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330018
System and method to process a virtual partition cell injected into a hierarchical integrated circuit design May 24, 2021 Issued
Array ( [id] => 18839324 [patent_doc_number] => 11847398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Automatic generation of ground rule verification macros [patent_app_type] => utility [patent_app_number] => 17/303170 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303170 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303170
Automatic generation of ground rule verification macros May 20, 2021 Issued
Array ( [id] => 18430733 [patent_doc_number] => 11675955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-13 [patent_title] => Routing using rule-based blockage extension [patent_app_type] => utility [patent_app_number] => 17/303052 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303052 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303052
Routing using rule-based blockage extension May 18, 2021 Issued
Array ( [id] => 17484745 [patent_doc_number] => 20220092249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/324829 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/324829
Semiconductor device May 18, 2021 Issued
Array ( [id] => 17992241 [patent_doc_number] => 20220358278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SYSTEMS AND METHODS FOR ELIMINATING ELECTROMIGRATION AND SELF-HEAT VIOLATIONS IN A MASK LAYOUT BLOCK [patent_app_type] => utility [patent_app_number] => 17/315747 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315747
Systems and methods for eliminating electromigration and self-heat violations in a mask layout block May 9, 2021 Issued
Array ( [id] => 18577952 [patent_doc_number] => 11734485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-22 [patent_title] => Routing congestion based on fractional via cost and via density [patent_app_type] => utility [patent_app_number] => 17/314932 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314932
Routing congestion based on fractional via cost and via density May 6, 2021 Issued
Array ( [id] => 19887070 [patent_doc_number] => 12272805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => System and method for cooling battery cells [patent_app_type] => utility [patent_app_number] => 17/314547 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314547
System and method for cooling battery cells May 6, 2021 Issued
Array ( [id] => 19123951 [patent_doc_number] => 11967952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Electronic system including FPGA and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/242737 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242737
Electronic system including FPGA and operation method thereof Apr 27, 2021 Issued
Array ( [id] => 17276853 [patent_doc_number] => 20210383051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => Automatic Identification Of Hierarchical Cells Based On Selected Properties For Layout Verification [patent_app_type] => utility [patent_app_number] => 17/241694 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241694 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241694
Automatic identification of hierarchical cells based on selected properties for layout verification Apr 26, 2021 Issued
Array ( [id] => 17172838 [patent_doc_number] => 20210326508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => LAYOUT OF PHOTONIC INTEGRATED CIRCUITS USING FIXED COORDINATE GRIDS [patent_app_type] => utility [patent_app_number] => 17/233343 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233343 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233343
Layout of photonic integrated circuits using fixed coordinate grids Apr 15, 2021 Issued
Array ( [id] => 17948178 [patent_doc_number] => 20220335197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => Post-Routing Congestion Optimization [patent_app_type] => utility [patent_app_number] => 17/232491 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232491
Post-routing congestion optimization Apr 15, 2021 Issued
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