Search

Gregory J. Vaughn

Examiner (ID: 10261, Phone: (571)272-4131 , Office: P/2178 )

Most Active Art Unit
2178
Art Unit(s)
2178
Total Applications
438
Issued Applications
301
Pending Applications
15
Abandoned Applications
128

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19459935 [patent_doc_number] => 12100436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Method and system to balance ground bounce [patent_app_type] => utility [patent_app_number] => 18/321552 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321552
Method and system to balance ground bounce May 21, 2023 Issued
Array ( [id] => 19900033 [patent_doc_number] => 12277965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Memory structure and method for operating the same [patent_app_type] => utility [patent_app_number] => 18/319513 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319513
Memory structure and method for operating the same May 17, 2023 Issued
Array ( [id] => 19574862 [patent_doc_number] => 20240379154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => TRACKING WORST CASE MEMORY CELLS BY SUPPRESSING TRACKING WORDLINE VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/315619 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315619
TRACKING WORST CASE MEMORY CELLS BY SUPPRESSING TRACKING WORDLINE VOLTAGE May 10, 2023 Pending
Array ( [id] => 19204604 [patent_doc_number] => 20240176503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION ACCORDING TO INCREMENTAL STEP PULSE PROGRAMMING METHOD, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/312459 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312459
Memory device for performing program operation according to incremental step pulse programming method, storage device including the same, and operating method of the memory device May 3, 2023 Issued
Array ( [id] => 19204604 [patent_doc_number] => 20240176503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION ACCORDING TO INCREMENTAL STEP PULSE PROGRAMMING METHOD, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/312459 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312459
Memory device for performing program operation according to incremental step pulse programming method, storage device including the same, and operating method of the memory device May 3, 2023 Issued
Array ( [id] => 19204604 [patent_doc_number] => 20240176503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION ACCORDING TO INCREMENTAL STEP PULSE PROGRAMMING METHOD, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/312459 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312459
Memory device for performing program operation according to incremental step pulse programming method, storage device including the same, and operating method of the memory device May 3, 2023 Issued
Array ( [id] => 19204604 [patent_doc_number] => 20240176503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION ACCORDING TO INCREMENTAL STEP PULSE PROGRAMMING METHOD, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/312459 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312459
Memory device for performing program operation according to incremental step pulse programming method, storage device including the same, and operating method of the memory device May 3, 2023 Issued
Array ( [id] => 19544912 [patent_doc_number] => 20240361948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => BOOSTED DRIVER CIRCUITRY OF A LOW VOLTAGE SUPPLY MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/141229 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141229 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141229
Boosted driver circuitry of a low voltage supply memory controller Apr 27, 2023 Issued
Array ( [id] => 19544912 [patent_doc_number] => 20240361948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => BOOSTED DRIVER CIRCUITRY OF A LOW VOLTAGE SUPPLY MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/141229 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141229 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141229
Boosted driver circuitry of a low voltage supply memory controller Apr 27, 2023 Issued
Array ( [id] => 19544912 [patent_doc_number] => 20240361948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => BOOSTED DRIVER CIRCUITRY OF A LOW VOLTAGE SUPPLY MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/141229 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141229 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141229
Boosted driver circuitry of a low voltage supply memory controller Apr 27, 2023 Issued
Array ( [id] => 19912364 [patent_doc_number] => 12288582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Semiconductor memory device and method for compensating slew rate using impedance calibration [patent_app_type] => utility [patent_app_number] => 18/306987 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306987 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306987
Semiconductor memory device and method for compensating slew rate using impedance calibration Apr 24, 2023 Issued
Array ( [id] => 19398716 [patent_doc_number] => 12073082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => High capacity memory circuit with low effective latency [patent_app_type] => utility [patent_app_number] => 18/306073 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 15047 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306073 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306073
High capacity memory circuit with low effective latency Apr 23, 2023 Issued
Array ( [id] => 18905777 [patent_doc_number] => 20240021262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => APPARATUS WITH ADJUSTABLE DIAGNOSTIC MECHANISM AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/137388 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137388 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/137388
Apparatus with adjustable diagnostic mechanism and methods for operating the same Apr 19, 2023 Issued
Array ( [id] => 19191150 [patent_doc_number] => 20240170063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => CONTENT ADDRESSABLE MEMORY ARRAY DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/301440 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301440
Content addressable memory array device structure Apr 16, 2023 Issued
Array ( [id] => 19191150 [patent_doc_number] => 20240170063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => CONTENT ADDRESSABLE MEMORY ARRAY DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/301440 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301440
Content addressable memory array device structure Apr 16, 2023 Issued
Array ( [id] => 20389112 [patent_doc_number] => 12488845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Apparatus and method for programming and verifying data in non-volatile memory device [patent_app_type] => utility [patent_app_number] => 18/295855 [patent_app_country] => US [patent_app_date] => 2023-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6439 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295855
Apparatus and method for programming and verifying data in non-volatile memory device Apr 4, 2023 Issued
Array ( [id] => 20389112 [patent_doc_number] => 12488845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Apparatus and method for programming and verifying data in non-volatile memory device [patent_app_type] => utility [patent_app_number] => 18/295855 [patent_app_country] => US [patent_app_date] => 2023-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6439 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295855
Apparatus and method for programming and verifying data in non-volatile memory device Apr 4, 2023 Issued
Array ( [id] => 19926002 [patent_doc_number] => 12300294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Cantilever nanoelectromechanical decoder circuit and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/295276 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295276 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295276
Cantilever nanoelectromechanical decoder circuit and methods for forming the same Apr 3, 2023 Issued
Array ( [id] => 18743116 [patent_doc_number] => 20230352104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/191858 [patent_app_country] => US [patent_app_date] => 2023-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18191858 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/191858
NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF Mar 27, 2023 Pending
Array ( [id] => 19046470 [patent_doc_number] => 11935589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Bit line pre-charge circuit for power management modes in multi bank SRAM [patent_app_type] => utility [patent_app_number] => 18/188523 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18188523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/188523
Bit line pre-charge circuit for power management modes in multi bank SRAM Mar 22, 2023 Issued
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