Search

Gregory John Binda

Examiner (ID: 8769, Phone: (571)272-7077 , Office: P/3679 )

Most Active Art Unit
3679
Art Unit(s)
3679, 3629, 3626
Total Applications
3008
Issued Applications
2314
Pending Applications
175
Abandoned Applications
558

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13485315 [patent_doc_number] => 20180294200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => WAFER BASED CORROSION & TIME DEPENDENT CHEMICAL EFFECTS [patent_app_type] => utility [patent_app_number] => 15/480337 [patent_app_country] => US [patent_app_date] => 2017-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5896 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15480337 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/480337
Wafer based corrosion and time dependent chemical effects Apr 4, 2017 Issued
Array ( [id] => 13293511 [patent_doc_number] => 10157956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Method of monolithic integration of hyperspectral image sensor [patent_app_type] => utility [patent_app_number] => 15/477191 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 50 [patent_no_of_words] => 8303 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477191 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477191
Method of monolithic integration of hyperspectral image sensor Apr 2, 2017 Issued
Array ( [id] => 13145635 [patent_doc_number] => 10090156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Method for forming semiconductor structure having stress layers [patent_app_type] => utility [patent_app_number] => 15/477250 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477250 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477250
Method for forming semiconductor structure having stress layers Apr 2, 2017 Issued
Array ( [id] => 11990308 [patent_doc_number] => 20170294463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'PEELING METHOD AND MANUFACTURING METHOD OF FLEXIBLE DEVICE' [patent_app_type] => utility [patent_app_number] => 15/477528 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 23997 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477528
Peeling method and manufacturing method of flexible device Apr 2, 2017 Issued
Array ( [id] => 14984933 [patent_doc_number] => 10446387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Apparatus and method to control etch rate through adaptive spiking of chemistry [patent_app_type] => utility [patent_app_number] => 15/477863 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 12164 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477863
Apparatus and method to control etch rate through adaptive spiking of chemistry Apr 2, 2017 Issued
Array ( [id] => 11974704 [patent_doc_number] => 20170278858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-28 [patent_title] => 'MONOLITHIC 3-D DYNAMIC MEMORY AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/465556 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3209 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465556 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/465556
MONOLITHIC 3-D DYNAMIC MEMORY AND METHOD Mar 20, 2017 Abandoned
Array ( [id] => 12263917 [patent_doc_number] => 20180083113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'FABRICATION OF NANO-SHEET TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES' [patent_app_type] => utility [patent_app_number] => 15/462372 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462372 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462372
Fabrication of nano-sheet transistors with different threshold voltages Mar 16, 2017 Issued
Array ( [id] => 13769771 [patent_doc_number] => 10177235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Nano-sheet transistors with different threshold voltages [patent_app_type] => utility [patent_app_number] => 15/462447 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9411 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462447
Nano-sheet transistors with different threshold voltages Mar 16, 2017 Issued
Array ( [id] => 11673995 [patent_doc_number] => 20170162719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/440427 [patent_app_country] => US [patent_app_date] => 2017-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 32732 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440427 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/440427
Method for manufacturing oxide semiconductor device Feb 22, 2017 Issued
Array ( [id] => 11652760 [patent_doc_number] => 20170148661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'ZIG-ZAG TRENCH STRUCTURE TO PREVENT ASPECT RATIO TRAPPING DEFECT ESCAPE' [patent_app_type] => utility [patent_app_number] => 15/425338 [patent_app_country] => US [patent_app_date] => 2017-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3598 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15425338 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/425338
Forming zig-zag trench structure to prevent aspect ratio trapping defect escape Feb 5, 2017 Issued
Array ( [id] => 17196204 [patent_doc_number] => 11164971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Vertical SiC MOSFET [patent_app_type] => utility [patent_app_number] => 16/086212 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6325 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/086212
Vertical SiC MOSFET Jan 29, 2017 Issued
Array ( [id] => 16552980 [patent_doc_number] => 10886145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Production of a multi-chip component [patent_app_type] => utility [patent_app_number] => 16/072993 [patent_app_country] => US [patent_app_date] => 2017-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 12736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16072993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/072993
Production of a multi-chip component Jan 25, 2017 Issued
Array ( [id] => 13879227 [patent_doc_number] => 20190035954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => SEMICONDUCTOR STACKED BODY, LIGHT-RECEIVING ELEMENT, AND METHOD FOR PRODUCING SEMICONDUCTOR STACKED BODY [patent_app_type] => utility [patent_app_number] => 16/073039 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10122 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16073039 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/073039
Semiconductor stacked body, light-receiving element, and method for producing semiconductor stacked body Jan 23, 2017 Issued
Array ( [id] => 14460119 [patent_doc_number] => 10326034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Semiconductor laminate and light-receiving element [patent_app_type] => utility [patent_app_number] => 16/073006 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8150 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16073006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/073006
Semiconductor laminate and light-receiving element Jan 23, 2017 Issued
Array ( [id] => 13879131 [patent_doc_number] => 20190035906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => Field Effect Transistor and Method for Manufacturing Same [patent_app_type] => utility [patent_app_number] => 16/073148 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16073148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/073148
Field Effect Transistor and Method for Manufacturing Same Jan 17, 2017 Abandoned
Array ( [id] => 12026961 [patent_doc_number] => 20170317060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD' [patent_app_type] => utility [patent_app_number] => 15/365529 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365529
Semiconductor device having die pad Nov 29, 2016 Issued
Array ( [id] => 16067677 [patent_doc_number] => 10692802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Flexible semiconductor device with graphene tape [patent_app_type] => utility [patent_app_number] => 15/365549 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 3665 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365549 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365549
Flexible semiconductor device with graphene tape Nov 29, 2016 Issued
Array ( [id] => 12012649 [patent_doc_number] => 09805970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Method for forming deep trench spacing isolation for CMOS image sensors' [patent_app_type] => utility [patent_app_number] => 15/364955 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 8618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364955 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364955
Method for forming deep trench spacing isolation for CMOS image sensors Nov 29, 2016 Issued
Array ( [id] => 14177817 [patent_doc_number] => 10262929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Semiconductor device with lead frame [patent_app_type] => utility [patent_app_number] => 15/365525 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 5632 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365525
Semiconductor device with lead frame Nov 29, 2016 Issued
Array ( [id] => 15015545 [patent_doc_number] => 10453933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Barrier layer for dielectric layers in semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/336136 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15336136 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/336136
Barrier layer for dielectric layers in semiconductor devices Oct 26, 2016 Issued
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