Search

Gregory T. Prather

Examiner (ID: 17269, Phone: (571)270-5412 , Office: P/3658 )

Most Active Art Unit
3658
Art Unit(s)
4127, 3658, 3618, 3656
Total Applications
652
Issued Applications
437
Pending Applications
56
Abandoned Applications
182

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18376410 [patent_doc_number] => 20230151494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => CHAMBER WALL POLYMER PROTECTION SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/679537 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679537 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679537
Chamber wall polymer protection system and method Feb 23, 2022 Issued
Array ( [id] => 18227730 [patent_doc_number] => 20230066724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SPECTROSCOPIC ANALYSIS METHOD, METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME, AND SUBSTRATE PROCESS SYSTEM USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/673903 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673903
Spectroscopic analysis method, method for fabricating semiconductor device using the same, and substrate process system using the same Feb 16, 2022 Issued
Array ( [id] => 18570426 [patent_doc_number] => 20230260763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => SEMICONDUCTOR MANUFACTURING CHAMBER WITH PLASMA/GAS FLOW CONTROL DEVICE [patent_app_type] => utility [patent_app_number] => 17/671646 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671646 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671646
Semiconductor manufacturing chamber with plasma/gas flow control device Feb 14, 2022 Issued
Array ( [id] => 18540784 [patent_doc_number] => 20230245895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => SIDEWALL PASSIVATION FOR PLASMA ETCHING [patent_app_type] => utility [patent_app_number] => 17/590084 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/590084
Sidewall passivation for plasma etching Jan 31, 2022 Issued
Array ( [id] => 19420922 [patent_doc_number] => 20240297046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => ETCHING METHOD [patent_app_type] => utility [patent_app_number] => 18/025442 [patent_app_country] => US [patent_app_date] => 2022-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18025442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/025442
ETCHING METHOD Jan 31, 2022 Pending
Array ( [id] => 17780090 [patent_doc_number] => 20220246440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/586251 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17586251 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/586251
Substrate processing method and substrate processing apparatus Jan 26, 2022 Issued
Array ( [id] => 18500278 [patent_doc_number] => 20230223063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => SEMICONDUCTOR MEMORY STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/571945 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571945
Semiconductor memory structure and method for forming the semiconductor memory structure Jan 9, 2022 Issued
Array ( [id] => 19900176 [patent_doc_number] => 12278110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Bias voltage modulation approach for SiO/SiN layer alternating etch process [patent_app_type] => utility [patent_app_number] => 17/572397 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572397
Bias voltage modulation approach for SiO/SiN layer alternating etch process Jan 9, 2022 Issued
Array ( [id] => 19828726 [patent_doc_number] => 12249517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Manufacturing method of semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/646487 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4810 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646487
Manufacturing method of semiconductor structure Dec 29, 2021 Issued
Array ( [id] => 19886835 [patent_doc_number] => 12272562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Oxygen and iodine-containing hydrofluorocarbon compound for etching semiconductor structures [patent_app_type] => utility [patent_app_number] => 17/555094 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 15253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555094 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555094
Oxygen and iodine-containing hydrofluorocarbon compound for etching semiconductor structures Dec 16, 2021 Issued
Array ( [id] => 18439922 [patent_doc_number] => 20230187217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH PATTERNS HAVING DIFFERENT HEIGHTS [patent_app_type] => utility [patent_app_number] => 17/550317 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550317
Method for preparing semiconductor device structure with patterns having different heights Dec 13, 2021 Issued
Array ( [id] => 17692117 [patent_doc_number] => 20220199410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => CONFORMAL AMORPHOUS CARBON LAYER ETCH WITH SIDE-WALL PASSIVATION [patent_app_type] => utility [patent_app_number] => 17/550182 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550182
CONFORMAL AMORPHOUS CARBON LAYER ETCH WITH SIDE-WALL PASSIVATION Dec 13, 2021 Abandoned
Array ( [id] => 18265946 [patent_doc_number] => 20230087188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/644154 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644154
PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Dec 13, 2021 Abandoned
Array ( [id] => 19071040 [patent_doc_number] => 20240105466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => METHOD FOR FORMING PATTERN OF METAL OXIDE AND METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/273605 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18273605 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/273605
METHOD FOR FORMING PATTERN OF METAL OXIDE AND METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT Dec 13, 2021 Pending
Array ( [id] => 18439923 [patent_doc_number] => 20230187218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH ISOLATION PATTERNS HAVING DIFFERENT HEIGHTS [patent_app_type] => utility [patent_app_number] => 17/550321 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550321
Method for preparing semiconductor device structure with isolation patterns having different heights Dec 13, 2021 Issued
Array ( [id] => 19079442 [patent_doc_number] => 11948818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Temperature calibration with deposition and etch process [patent_app_type] => utility [patent_app_number] => 17/546769 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546769 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546769
Temperature calibration with deposition and etch process Dec 8, 2021 Issued
Array ( [id] => 18967411 [patent_doc_number] => 11901191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Atomic layer etching method and semiconductor device manufacturing method using the same [patent_app_type] => utility [patent_app_number] => 17/535933 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 10913 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535933
Atomic layer etching method and semiconductor device manufacturing method using the same Nov 25, 2021 Issued
Array ( [id] => 17963547 [patent_doc_number] => 20220344128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/532026 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532026
Substrate processing method and substrate processing apparatus Nov 21, 2021 Issued
Array ( [id] => 17963547 [patent_doc_number] => 20220344128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/532026 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532026
Substrate processing method and substrate processing apparatus Nov 21, 2021 Issued
Array ( [id] => 17963547 [patent_doc_number] => 20220344128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/532026 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532026
Substrate processing method and substrate processing apparatus Nov 21, 2021 Issued
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