
Guerrier Merant
Examiner (ID: 43, Phone: (571)270-1066 , Office: P/2117 )
| Most Active Art Unit | 2117 |
| Art Unit(s) | 2138, 2111, 2117 |
| Total Applications | 1514 |
| Issued Applications | 1294 |
| Pending Applications | 90 |
| Abandoned Applications | 150 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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Array
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Array
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Array
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Array
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Array
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Array
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