Search

Guerrier Merant

Examiner (ID: 43, Phone: (571)270-1066 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2138, 2111, 2117
Total Applications
1514
Issued Applications
1294
Pending Applications
90
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18170054 [patent_doc_number] => 20230036665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => Scan Testing in a Processor [patent_app_type] => utility [patent_app_number] => 17/814396 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814396
Scan testing in a processor Jul 21, 2022 Issued
Array ( [id] => 18220100 [patent_doc_number] => 11595057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Reducing error in data compression [patent_app_type] => utility [patent_app_number] => 17/863017 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8606 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863017
Reducing error in data compression Jul 11, 2022 Issued
Array ( [id] => 17962175 [patent_doc_number] => 20220342756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => STORAGE SYSTEM SPANNING MULTIPLE FAILURE DOMAINS [patent_app_type] => utility [patent_app_number] => 17/861651 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861651
Storage system spanning multiple failure domains Jul 10, 2022 Issued
Array ( [id] => 18933910 [patent_doc_number] => 11886338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Forwarding code word address [patent_app_type] => utility [patent_app_number] => 17/861018 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861018 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861018
Forwarding code word address Jul 7, 2022 Issued
Array ( [id] => 17950253 [patent_doc_number] => 20220337272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => CONVOLUTIONAL CODE RATE MATCHING METHOD AND WIRELESS COMMUNICATION APPARATUS [patent_app_type] => utility [patent_app_number] => 17/856773 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/856773
Convolutional code rate matching method and wireless communication apparatus Jun 30, 2022 Issued
Array ( [id] => 18584772 [patent_doc_number] => 20230267036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => DATA TRANSMISSION CIRCUIT AND DATA TRANSMISSION METHOD [patent_app_type] => utility [patent_app_number] => 17/810015 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810015
Data transmission circuit and data transmission method Jun 29, 2022 Issued
Array ( [id] => 19106872 [patent_doc_number] => 11959965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same [patent_app_type] => utility [patent_app_number] => 17/851860 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851860
Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same Jun 27, 2022 Issued
Array ( [id] => 20667385 [patent_doc_number] => 12609165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Method for detecting an error in an electronic memory [patent_app_type] => utility [patent_app_number] => 18/686175 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 41 [patent_no_of_words] => 5306 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18686175 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/686175
Method for detecting an error in an electronic memory Jun 19, 2022 Issued
Array ( [id] => 19080043 [patent_doc_number] => 11949428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Iterative error correction in memory systems [patent_app_type] => utility [patent_app_number] => 17/843171 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8339 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843171 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/843171
Iterative error correction in memory systems Jun 16, 2022 Issued
Array ( [id] => 17871738 [patent_doc_number] => 20220294475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => PARITY INTERLEAVING APPARATUS FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND PARITY INTERLEAVING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 17/830410 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830410
Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same Jun 1, 2022 Issued
Array ( [id] => 19028665 [patent_doc_number] => 11928022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Introduction and detection of parity error in a UART [patent_app_type] => utility [patent_app_number] => 17/825277 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7244 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17825277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/825277
Introduction and detection of parity error in a UART May 25, 2022 Issued
Array ( [id] => 18615562 [patent_doc_number] => 20230282299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => CHIP TEST METHOD, APPARATUS, AND DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/664443 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664443
Chip test method, apparatus, and device, and storage medium May 22, 2022 Issued
Array ( [id] => 18387885 [patent_doc_number] => 11658683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Data processing device and data processing method [patent_app_type] => utility [patent_app_number] => 17/661981 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 230 [patent_figures_cnt] => 230 [patent_no_of_words] => 55281 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661981
Data processing device and data processing method May 3, 2022 Issued
Array ( [id] => 18356751 [patent_doc_number] => 11645152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Energy efficient storage of error-correction-detection information [patent_app_type] => utility [patent_app_number] => 17/734464 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734464 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734464
Energy efficient storage of error-correction-detection information May 1, 2022 Issued
Array ( [id] => 18220101 [patent_doc_number] => 11595058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-28 [patent_title] => Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells [patent_app_type] => utility [patent_app_number] => 17/733724 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3452 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733724
Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells Apr 28, 2022 Issued
Array ( [id] => 19137862 [patent_doc_number] => 11972833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Calibration circuit and semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 17/732439 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8824 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732439
Calibration circuit and semiconductor device including the same Apr 27, 2022 Issued
Array ( [id] => 18669679 [patent_doc_number] => 11776589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Vertical compression scheme for compressed soft bit data in non-volatile memories with data latch groups [patent_app_type] => utility [patent_app_number] => 17/731961 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 52 [patent_no_of_words] => 30061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731961 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731961
Vertical compression scheme for compressed soft bit data in non-volatile memories with data latch groups Apr 27, 2022 Issued
Array ( [id] => 19398404 [patent_doc_number] => 12072765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Flexible RAID scheme allowing fast rebuild [patent_app_type] => utility [patent_app_number] => 17/730388 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730388
Flexible RAID scheme allowing fast rebuild Apr 26, 2022 Issued
Array ( [id] => 18826126 [patent_doc_number] => 11841398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Method and apparatus and non-transitory computer-readable storage medium for debugging solid-state disk (SSD) device [patent_app_type] => utility [patent_app_number] => 17/729574 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729574
Method and apparatus and non-transitory computer-readable storage medium for debugging solid-state disk (SSD) device Apr 25, 2022 Issued
Array ( [id] => 17869255 [patent_doc_number] => 20220291992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => Energy-Efficient Error-Correction-Detection Storage [patent_app_type] => utility [patent_app_number] => 17/721735 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721735 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721735
Energy-efficient error-correction-detection storage Apr 14, 2022 Issued
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