
Guinever S. Gregorio
Examiner (ID: 15367)
| Most Active Art Unit | 1732 |
| Art Unit(s) | 1732, 1793 |
| Total Applications | 935 |
| Issued Applications | 638 |
| Pending Applications | 63 |
| Abandoned Applications | 246 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19803711
[patent_doc_number] => 20250069636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-27
[patent_title] => FLASH MEMORY DEVICES INCLUDING DRAM
[patent_app_type] => utility
[patent_app_number] => 18/939609
[patent_app_country] => US
[patent_app_date] => 2024-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10367
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939609
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/939609 | FLASH MEMORY DEVICES INCLUDING DRAM | Nov 6, 2024 | Pending |
Array
(
[id] => 19757817
[patent_doc_number] => 20250046382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-06
[patent_title] => SEMICONDUCTOR MEMORY DEVICE WITH FIRST AND SECOND SENSE AMPLIFIERS
[patent_app_type] => utility
[patent_app_number] => 18/926712
[patent_app_country] => US
[patent_app_date] => 2024-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 32504
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 450
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926712
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/926712 | SEMICONDUCTOR MEMORY DEVICE WITH FIRST AND SECOND SENSE AMPLIFIERS | Oct 24, 2024 | Pending |
Array
(
[id] => 19893060
[patent_doc_number] => 20250118372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => WRITE LATENCY AND ENERGY USING ASYMMETRIC CELL DESIGN
[patent_app_type] => utility
[patent_app_number] => 18/913710
[patent_app_country] => US
[patent_app_date] => 2024-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15603
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18913710
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/913710 | WRITE LATENCY AND ENERGY USING ASYMMETRIC CELL DESIGN | Oct 10, 2024 | Pending |
Array
(
[id] => 19749193
[patent_doc_number] => 20250037758
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => VERTICAL MEMORY DEVICE WITH A DOUBLE WORD LINE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/911271
[patent_app_country] => US
[patent_app_date] => 2024-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11776
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18911271
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/911271 | VERTICAL MEMORY DEVICE WITH A DOUBLE WORD LINE STRUCTURE | Oct 9, 2024 | Pending |
Array
(
[id] => 19893078
[patent_doc_number] => 20250118390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => TEST DEVICE, OPERATING METHOD OF THE SAME, AND TEST SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/904629
[patent_app_country] => US
[patent_app_date] => 2024-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12987
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904629
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/904629 | TEST DEVICE, OPERATING METHOD OF THE SAME, AND TEST SYSTEM | Oct 1, 2024 | Pending |
Array
(
[id] => 20381553
[patent_doc_number] => 20250364046
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-27
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/904197
[patent_app_country] => US
[patent_app_date] => 2024-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904197
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/904197 | MEMORY DEVICE | Oct 1, 2024 | Pending |
Array
(
[id] => 20630355
[patent_doc_number] => 20260094643
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-04-02
[patent_title] => READ SIGNAL OUTPUT TERMINAL DRIVER
[patent_app_type] => utility
[patent_app_number] => 18/904495
[patent_app_country] => US
[patent_app_date] => 2024-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904495
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/904495 | READ SIGNAL OUTPUT TERMINAL DRIVER | Oct 1, 2024 | Pending |
Array
(
[id] => 20253048
[patent_doc_number] => 20250301917
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/894421
[patent_app_country] => US
[patent_app_date] => 2024-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1152
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894421
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/894421 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME | Sep 23, 2024 | Pending |
Array
(
[id] => 19687684
[patent_doc_number] => 20250006229
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/828820
[patent_app_country] => US
[patent_app_date] => 2024-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4835
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828820
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/828820 | SEMICONDUCTOR MEMORY DEVICE | Sep 8, 2024 | Pending |
Array
(
[id] => 19636477
[patent_doc_number] => 20240414926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => SEMICONDUCTOR DEVICE INCLUDING CHALCOGEN COMPOUND AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/813539
[patent_app_country] => US
[patent_app_date] => 2024-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10111
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813539
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/813539 | SEMICONDUCTOR DEVICE INCLUDING CHALCOGEN COMPOUND AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME | Aug 22, 2024 | Pending |
Array
(
[id] => 20053421
[patent_doc_number] => 20250191643
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-12
[patent_title] => SEMICONDUCTOR DEVICE HAVING DELAY LINE
[patent_app_type] => utility
[patent_app_number] => 18/780165
[patent_app_country] => US
[patent_app_date] => 2024-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18780165
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/780165 | SEMICONDUCTOR DEVICE HAVING DELAY LINE | Jul 21, 2024 | Pending |
Array
(
[id] => 20002085
[patent_doc_number] => 20250140307
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-01
[patent_title] => BIT LINE PRE-CHARGE VOLTAGE GENERATING CIRCUIT IN SEMICONDUCTOR MEMORY DEVICES FOR REDUCING CURRENT CONSUMPTION
[patent_app_type] => utility
[patent_app_number] => 18/778336
[patent_app_country] => US
[patent_app_date] => 2024-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4568
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 304
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778336
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/778336 | BIT LINE PRE-CHARGE VOLTAGE GENERATING CIRCUIT IN SEMICONDUCTOR MEMORY DEVICES FOR REDUCING CURRENT CONSUMPTION | Jul 18, 2024 | Pending |
Array
(
[id] => 19559630
[patent_doc_number] => 20240371422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => DATA RECEIVING CIRCUIT FOR CHIPLET BASED STORAGE ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 18/773410
[patent_app_country] => US
[patent_app_date] => 2024-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18984
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773410
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/773410 | DATA RECEIVING CIRCUIT FOR CHIPLET BASED STORAGE ARCHITECTURES | Jul 14, 2024 | Pending |
Array
(
[id] => 20461946
[patent_doc_number] => 20260011375
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-08
[patent_title] => MEMORY DEVICE AND OPERATING METHOD FOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/761315
[patent_app_country] => US
[patent_app_date] => 2024-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761315
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/761315 | MEMORY DEVICE AND OPERATING METHOD FOR MEMORY DEVICE | Jul 1, 2024 | Pending |
Array
(
[id] => 20102854
[patent_doc_number] => 20250232790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-17
[patent_title] => RACETRACK MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/760609
[patent_app_country] => US
[patent_app_date] => 2024-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4822
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760609
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/760609 | RACETRACK MEMORY DEVICE | Jun 30, 2024 | Pending |
Array
(
[id] => 20429378
[patent_doc_number] => 20250391471
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-25
[patent_title] => CAPACITOR FOR SNAPBACK CURRENT MITIGATION
[patent_app_type] => utility
[patent_app_number] => 18/749383
[patent_app_country] => US
[patent_app_date] => 2024-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12055
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749383
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/749383 | CAPACITOR FOR SNAPBACK CURRENT MITIGATION | Jun 19, 2024 | Pending |
Array
(
[id] => 19648472
[patent_doc_number] => 20240422992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-19
[patent_title] => MEMORY CIRCUIT COMPRISING ELECTRONIC CELLS AND A CONTROL CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/738675
[patent_app_country] => US
[patent_app_date] => 2024-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5193
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738675
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/738675 | MEMORY CIRCUIT COMPRISING ELECTRONIC CELLS AND A CONTROL CIRCUIT | Jun 9, 2024 | Pending |
Array
(
[id] => 19467680
[patent_doc_number] => 20240321350
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => REFRESH OF NEIGHBORING MEMORY CELLS BASED ON READ STATUS
[patent_app_type] => utility
[patent_app_number] => 18/734724
[patent_app_country] => US
[patent_app_date] => 2024-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9606
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734724
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/734724 | REFRESH OF NEIGHBORING MEMORY CELLS BASED ON READ STATUS | Jun 4, 2024 | Pending |
Array
(
[id] => 20396710
[patent_doc_number] => 20250372185
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => FAKE FAST PLANE DETECTION IN EARLY PROGRAM TERMINATION
[patent_app_type] => utility
[patent_app_number] => 18/680066
[patent_app_country] => US
[patent_app_date] => 2024-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13251
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680066
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/680066 | Fake fast plane detection in early program termination | May 30, 2024 | Issued |
Array
(
[id] => 20396691
[patent_doc_number] => 20250372166
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-04
[patent_title] => ERASE ALGORITHM FOR NON-VOLATILE MEMORY DEFINING A WEAK PROGRAM STATE AS AN ERASE STATE
[patent_app_type] => utility
[patent_app_number] => 18/678273
[patent_app_country] => US
[patent_app_date] => 2024-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8468
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678273
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/678273 | ERASE ALGORITHM FOR NON-VOLATILE MEMORY DEFINING A WEAK PROGRAM STATE AS AN ERASE STATE | May 29, 2024 | Pending |