
Guinever S. Gregorio
Examiner (ID: 15367)
| Most Active Art Unit | 1732 |
| Art Unit(s) | 1732, 1793 |
| Total Applications | 935 |
| Issued Applications | 638 |
| Pending Applications | 63 |
| Abandoned Applications | 246 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20674068
[patent_doc_number] => 12614588
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-28
[patent_title] => Optical property storage device and system using same
[patent_app_type] => utility
[patent_app_number] => 18/564258
[patent_app_country] => US
[patent_app_date] => 2022-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 10288
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18564258
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/564258 | Optical property storage device and system using same | Apr 6, 2022 | Issued |
Array
(
[id] => 18495352
[patent_doc_number] => 11700779
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Method of forming phase-change memory layers on recessed electrodes
[patent_app_type] => utility
[patent_app_number] => 17/657777
[patent_app_country] => US
[patent_app_date] => 2022-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7402
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657777
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/657777 | Method of forming phase-change memory layers on recessed electrodes | Apr 3, 2022 | Issued |
Array
(
[id] => 20636575
[patent_doc_number] => 12597456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Field-programmable ferro-diodes for reconfigurable in-memory-computing
[patent_app_type] => utility
[patent_app_number] => 18/553253
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 42
[patent_no_of_words] => 9050
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18553253
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/553253 | Field-programmable ferro-diodes for reconfigurable in-memory-computing | Mar 29, 2022 | Issued |
Array
(
[id] => 18679498
[patent_doc_number] => 20230317154
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => TECHNOLOGIES FOR DYNAMIC BIASING FOR MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 17/706943
[patent_app_country] => US
[patent_app_date] => 2022-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13998
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706943
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/706943 | TECHNOLOGIES FOR DYNAMIC BIASING FOR MEMORY CELLS | Mar 28, 2022 | Pending |
Array
(
[id] => 17708241
[patent_doc_number] => 20220208249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => PROCESSING IN MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/694184
[patent_app_country] => US
[patent_app_date] => 2022-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14736
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694184
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/694184 | Processing in memory implementing VLIW controller | Mar 13, 2022 | Issued |
Array
(
[id] => 18631501
[patent_doc_number] => 20230290403
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-14
[patent_title] => LOW POWER MODE WITH READ SEQUENCE ADJUSTMENT
[patent_app_type] => utility
[patent_app_number] => 17/690332
[patent_app_country] => US
[patent_app_date] => 2022-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11672
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690332
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/690332 | Low power mode with read sequence adjustment | Mar 8, 2022 | Issued |
Array
(
[id] => 18266092
[patent_doc_number] => 20230087334
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => SEMICONDUCTOR STORAGE DEVICE AND DATA ERASING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/682968
[patent_app_country] => US
[patent_app_date] => 2022-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12047
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682968
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/682968 | Semiconductor storage device and data erasing method | Feb 27, 2022 | Issued |
Array
(
[id] => 17795907
[patent_doc_number] => 20220254999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-11
[patent_title] => MEMORY DEVICE WITH INCREASED ELECTRODE RESISTANCE TO REDUCE TRANSIENT SELECTION CURRENT
[patent_app_type] => utility
[patent_app_number] => 17/682297
[patent_app_country] => US
[patent_app_date] => 2022-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9020
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682297
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/682297 | MEMORY DEVICE WITH INCREASED ELECTRODE RESISTANCE TO REDUCE TRANSIENT SELECTION CURRENT | Feb 27, 2022 | Abandoned |
Array
(
[id] => 19384308
[patent_doc_number] => 20240274178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-15
[patent_title] => STORAGE DEVICE, MEMORY CELL ARRAY, METHOD FOR MANUFACTURING MEMORY CELL ARRAY, MAGNETIC HEAD, AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/567789
[patent_app_country] => US
[patent_app_date] => 2022-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11358
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18567789
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/567789 | STORAGE DEVICE, MEMORY CELL ARRAY, METHOD FOR MANUFACTURING MEMORY CELL ARRAY, MAGNETIC HEAD, AND ELECTRONIC DEVICE | Feb 23, 2022 | Pending |
Array
(
[id] => 19813995
[patent_doc_number] => 12245425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
[patent_app_type] => utility
[patent_app_number] => 17/673137
[patent_app_country] => US
[patent_app_date] => 2022-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 56
[patent_no_of_words] => 22805
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673137
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/673137 | Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof | Feb 15, 2022 | Issued |
Array
(
[id] => 18570236
[patent_doc_number] => 20230260573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-17
[patent_title] => SPIKE BASED PROGRAMMING OF A MEMORY CELL TO RESET STATE
[patent_app_type] => utility
[patent_app_number] => 17/671091
[patent_app_country] => US
[patent_app_date] => 2022-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14224
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671091
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/671091 | Spike based programming of a memory cell to reset state | Feb 13, 2022 | Issued |
Array
(
[id] => 19582337
[patent_doc_number] => 12148463
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-19
[patent_title] => Dual port memory cell with multiple metal layers
[patent_app_type] => utility
[patent_app_number] => 17/671288
[patent_app_country] => US
[patent_app_date] => 2022-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 17625
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671288
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/671288 | Dual port memory cell with multiple metal layers | Feb 13, 2022 | Issued |
Array
(
[id] => 17582617
[patent_doc_number] => 20220139472
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => MULTI-GATE NOR FLASH THIN-FILM TRANSISTOR STRINGS ARRANGED IN STACKED HORIZONTAL ACTIVE STRIPS WITH VERTICAL CONTROL GATES
[patent_app_type] => utility
[patent_app_number] => 17/579364
[patent_app_country] => US
[patent_app_date] => 2022-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12104
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17579364
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/579364 | Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates | Jan 18, 2022 | Issued |
Array
(
[id] => 19764545
[patent_doc_number] => 12222835
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => Systems and methods to manage memory during power down and storage
[patent_app_type] => utility
[patent_app_number] => 17/575399
[patent_app_country] => US
[patent_app_date] => 2022-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 9043
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575399
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/575399 | Systems and methods to manage memory during power down and storage | Jan 12, 2022 | Issued |
Array
(
[id] => 17551334
[patent_doc_number] => 20220122676
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => ADJUSTING PROGRAM EFFECTIVE TIME USING PROGRAM STEP CHARACTERISTICS
[patent_app_type] => utility
[patent_app_number] => 17/561278
[patent_app_country] => US
[patent_app_date] => 2021-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7315
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561278
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/561278 | Adjusting program effective time using program step characteristics | Dec 22, 2021 | Issued |
Array
(
[id] => 17985740
[patent_doc_number] => 20220351777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/552225
[patent_app_country] => US
[patent_app_date] => 2021-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19202
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552225
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/552225 | Semiconductor memory device | Dec 14, 2021 | Issued |
Array
(
[id] => 17676870
[patent_doc_number] => 20220190037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => MEMORY COMPRISING A MATRIX OF RESISTIVE MEMORY CELLS, AND ASSOCIATED METHOD OF INTERFACING
[patent_app_type] => utility
[patent_app_number] => 17/549162
[patent_app_country] => US
[patent_app_date] => 2021-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11497
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549162
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/549162 | Memory comprising a matrix of resistive memory cells, and associated method of interfacing | Dec 12, 2021 | Issued |
Array
(
[id] => 18431433
[patent_doc_number] => 11676660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Static random access memory with a supplementary driver circuit and method of controlling the same
[patent_app_type] => utility
[patent_app_number] => 17/541240
[patent_app_country] => US
[patent_app_date] => 2021-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 10608
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17541240
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/541240 | Static random access memory with a supplementary driver circuit and method of controlling the same | Dec 1, 2021 | Issued |
Array
(
[id] => 17932957
[patent_doc_number] => 20220328083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => MAGNETIC MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/537937
[patent_app_country] => US
[patent_app_date] => 2021-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13431
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537937
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/537937 | Magnetic memory device with a plurality of capping layers | Nov 29, 2021 | Issued |
Array
(
[id] => 17477089
[patent_doc_number] => 20220084593
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => METHOD OF RRAM WRITE RAMPING VOLTAGE IN INTERVALS
[patent_app_type] => utility
[patent_app_number] => 17/536386
[patent_app_country] => US
[patent_app_date] => 2021-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5688
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536386
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/536386 | Method of RRAM write ramping voltage in intervals | Nov 28, 2021 | Issued |