Search

Gurtej Bansal

Examiner (ID: 7379, Phone: (571)270-5588 , Office: P/2139 )

Most Active Art Unit
2139
Art Unit(s)
2139, 2189, 4173
Total Applications
770
Issued Applications
617
Pending Applications
9
Abandoned Applications
149

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16789224 [patent_doc_number] => 10991663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Semiconductor device including dummy conductive cells [patent_app_type] => utility [patent_app_number] => 16/714542 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714542 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714542
Semiconductor device including dummy conductive cells Dec 12, 2019 Issued
Array ( [id] => 16553074 [patent_doc_number] => 10886239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Customisation of an integrated circuit during the realisation thereof [patent_app_type] => utility [patent_app_number] => 16/667332 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5152 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667332
Customisation of an integrated circuit during the realisation thereof Oct 28, 2019 Issued
Array ( [id] => 16759848 [patent_doc_number] => 10978405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Integrated fan-out package [patent_app_type] => utility [patent_app_number] => 16/667838 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 46 [patent_no_of_words] => 13962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667838 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667838
Integrated fan-out package Oct 28, 2019 Issued
Array ( [id] => 15532621 [patent_doc_number] => 20200058616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => Redistribution Layers in Semiconductor Packages and Methods of Forming Same [patent_app_type] => utility [patent_app_number] => 16/661636 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661636 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661636
Redistribution layers in semiconductor packages and methods of forming same Oct 22, 2019 Issued
Array ( [id] => 15656923 [patent_doc_number] => 20200090992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => DECOUPLED VIA FILL [patent_app_type] => utility [patent_app_number] => 16/582923 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582923 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/582923
Decoupled via fill Sep 24, 2019 Issued
Array ( [id] => 15300089 [patent_doc_number] => 20190393180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE [patent_app_type] => utility [patent_app_number] => 16/561965 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561965 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561965
High density substrate routing in package Sep 4, 2019 Issued
Array ( [id] => 16264577 [patent_doc_number] => 10756022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings [patent_app_type] => utility [patent_app_number] => 16/554118 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 8291 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554118 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/554118
Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings Aug 27, 2019 Issued
Array ( [id] => 16233922 [patent_doc_number] => 10741485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Nanostructure energy storage and electronic device [patent_app_type] => utility [patent_app_number] => 16/550706 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6686 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550706 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550706
Nanostructure energy storage and electronic device Aug 25, 2019 Issued
Array ( [id] => 16536501 [patent_doc_number] => 10879114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Conductive fill [patent_app_type] => utility [patent_app_number] => 16/549256 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549256 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/549256
Conductive fill Aug 22, 2019 Issued
Array ( [id] => 16502497 [patent_doc_number] => 10867892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/548835 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 9628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548835 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548835
Semiconductor structure and manufacturing method thereof Aug 21, 2019 Issued
Array ( [id] => 16372459 [patent_doc_number] => 10804225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Power gate circuits for semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/532140 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16532140 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/532140
Power gate circuits for semiconductor devices Aug 4, 2019 Issued
Array ( [id] => 15154463 [patent_doc_number] => 20190355709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => PACKAGE ON PACKAGE WITH INTEGRATED PASSIVE ELECTRONICS METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 16/529348 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529348 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529348
Package on package with integrated passive electronics method and apparatus Jul 31, 2019 Issued
Array ( [id] => 15093131 [patent_doc_number] => 20190341377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => Hollow Metal Pillar Packaging Scheme [patent_app_type] => utility [patent_app_number] => 16/511454 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/511454
Hollow metal pillar packaging scheme Jul 14, 2019 Issued
Array ( [id] => 14938437 [patent_doc_number] => 20190304857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => Power Semiconductor Device Module Having Mechanical Corner Press-Fit Anchors [patent_app_type] => utility [patent_app_number] => 16/435485 [patent_app_country] => US [patent_app_date] => 2019-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435485 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/435485
Power Semiconductor Device Module Having Mechanical Corner Press-Fit Anchors Jun 7, 2019 Abandoned
Array ( [id] => 15218141 [patent_doc_number] => 20190371757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/426469 [patent_app_country] => US [patent_app_date] => 2019-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16426469 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/426469
Semiconductor device May 29, 2019 Issued
Array ( [id] => 16384804 [patent_doc_number] => 10809637 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Learning based digital corrections to compensate variations on lithography systems with multiple imaging units [patent_app_type] => utility [patent_app_number] => 16/426458 [patent_app_country] => US [patent_app_date] => 2019-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16426458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/426458
Learning based digital corrections to compensate variations on lithography systems with multiple imaging units May 29, 2019 Issued
Array ( [id] => 16645546 [patent_doc_number] => 10923413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Hard IP blocks with physically bidirectional passageways [patent_app_type] => utility [patent_app_number] => 16/426515 [patent_app_country] => US [patent_app_date] => 2019-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4961 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16426515 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/426515
Hard IP blocks with physically bidirectional passageways May 29, 2019 Issued
Array ( [id] => 15218287 [patent_doc_number] => 20190371830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => DOUBLE-SIDED ELECTRODE STRUCTURE AND PATTERNING PROCESS THEREOF [patent_app_type] => utility [patent_app_number] => 16/426102 [patent_app_country] => US [patent_app_date] => 2019-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16426102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/426102
Double-sided electrode structure and patterning process thereof May 29, 2019 Issued
Array ( [id] => 14812859 [patent_doc_number] => 20190273039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => SEMICONDUCTOR DEVICE HAVING FLEXIBLE INTERCONNECTION AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/413757 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413757 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413757
Semiconductor device having flexible interconnection and method for fabricating the same May 15, 2019 Issued
Array ( [id] => 15388763 [patent_doc_number] => 10535580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Thermal dissipation through seal rings in 3DIC structure [patent_app_type] => utility [patent_app_number] => 16/410489 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410489 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410489
Thermal dissipation through seal rings in 3DIC structure May 12, 2019 Issued
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