Search

Gustavo G. Ramallo

Examiner (ID: 486, Phone: (571)272-9227 , Office: P/2819 )

Most Active Art Unit
2819
Art Unit(s)
2826, 2812, 2819
Total Applications
699
Issued Applications
602
Pending Applications
85
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19591769 [patent_doc_number] => 20240389326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICES WITH DRAIN-SELECT-GATE CUT STRUCTURES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/785408 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785408 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785408
THREE-DIMENSIONAL MEMORY DEVICES WITH DRAIN-SELECT-GATE CUT STRUCTURES AND METHODS FOR FORMING THE SAME Jul 25, 2024 Pending
Array ( [id] => 19515937 [patent_doc_number] => 20240347623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => DIELECTRIC SPACER TO PREVENT CONTACTING SHORTING [patent_app_type] => utility [patent_app_number] => 18/753240 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753240 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753240
DIELECTRIC SPACER TO PREVENT CONTACTING SHORTING Jun 24, 2024 Pending
Array ( [id] => 19484154 [patent_doc_number] => 20240332196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/739930 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739930 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739930
INTEGRATED CIRCUIT DEVICE Jun 10, 2024 Pending
Array ( [id] => 20404474 [patent_doc_number] => 12494455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Multi-die package structures including an interconnected package component disposed in a substrate cavity [patent_app_type] => utility [patent_app_number] => 18/678141 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 8503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678141 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678141
Multi-die package structures including an interconnected package component disposed in a substrate cavity May 29, 2024 Issued
Array ( [id] => 19409121 [patent_doc_number] => 20240292632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => CROSS-POINT MEMORY ARRAY WITH ACCESS LINES [patent_app_type] => utility [patent_app_number] => 18/657259 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657259
Cross-point memory array with access lines May 6, 2024 Issued
Array ( [id] => 19422327 [patent_doc_number] => 20240298451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor [patent_app_type] => utility [patent_app_number] => 18/647122 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647122 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647122
Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor Apr 25, 2024 Pending
Array ( [id] => 19364442 [patent_doc_number] => 20240266476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => LIGHT-EMITTING ELEMENT [patent_app_type] => utility [patent_app_number] => 18/638220 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/638220
Light-emitting element with a cushion part Apr 16, 2024 Issued
Array ( [id] => 19517811 [patent_doc_number] => 20240349497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => INTEGRATED CIRCUIT INCLUDING READ ONLY MEMORY (ROM) CELL [patent_app_type] => utility [patent_app_number] => 18/637013 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637013 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637013
INTEGRATED CIRCUIT INCLUDING READ ONLY MEMORY (ROM) CELL Apr 15, 2024 Pending
Array ( [id] => 19335637 [patent_doc_number] => 20240250067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => MULTI-DIE PACKAGE STRUCTURES INCLUDING REDISTRIBUTION LAYERS [patent_app_type] => utility [patent_app_number] => 18/598250 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598250 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598250
MULTI-DIE PACKAGE STRUCTURES INCLUDING REDISTRIBUTION LAYERS Mar 6, 2024 Pending
Array ( [id] => 20223029 [patent_doc_number] => 20250285960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => SEMICONDUCTOR DEVICES HAVING A PATTERNED CONTACT [patent_app_type] => utility [patent_app_number] => 18/597966 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597966
SEMICONDUCTOR DEVICES HAVING A PATTERNED CONTACT Mar 6, 2024 Pending
Array ( [id] => 19688203 [patent_doc_number] => 20250006748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => Light Sensor Structure and Packaging Method thereof [patent_app_type] => utility [patent_app_number] => 18/597970 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18597970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/597970
Light Sensor Structure and Packaging Method thereof Mar 6, 2024 Pending
Array ( [id] => 19349198 [patent_doc_number] => 20240258162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => INTERCONNECTION STRUCTURE WITH ANTI-ADHESION LAYER [patent_app_type] => utility [patent_app_number] => 18/593752 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593752 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593752
Interconnection structure with anti-adhesion layer Feb 29, 2024 Issued
Array ( [id] => 19470493 [patent_doc_number] => 20240324163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/590867 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590867
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE Feb 27, 2024 Pending
Array ( [id] => 19900041 [patent_doc_number] => 12277973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Memory array comprising strings of memory cells and conductive gate lines of different vertical thicknesses [patent_app_type] => utility [patent_app_number] => 18/588407 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 2126 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18588407 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/588407
Memory array comprising strings of memory cells and conductive gate lines of different vertical thicknesses Feb 26, 2024 Issued
Array ( [id] => 19945324 [patent_doc_number] => 12317474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Method for forming memory device with buried gate in peripheral circuit region [patent_app_type] => utility [patent_app_number] => 18/442116 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3284 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442116 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442116
Method for forming memory device with buried gate in peripheral circuit region Feb 14, 2024 Issued
Array ( [id] => 19881325 [patent_doc_number] => 20250113582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/430672 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430672
SEMICONDUCTOR DEVICE Feb 1, 2024 Pending
Array ( [id] => 19176192 [patent_doc_number] => 20240162166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => THERMAL INTERFACE MATERIAL HAVING DIFFERENT THICKNESSES IN PACKAGES [patent_app_type] => utility [patent_app_number] => 18/422550 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422550 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/422550
THERMAL INTERFACE MATERIAL HAVING DIFFERENT THICKNESSES IN PACKAGES Jan 24, 2024 Pending
Array ( [id] => 20063509 [patent_doc_number] => 20250201731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/416854 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416854
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Jan 17, 2024 Pending
Array ( [id] => 20088827 [patent_doc_number] => 20250218763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => TREATING SILICON NITRIDE BASED DIELECTRIC FILMS [patent_app_type] => utility [patent_app_number] => 18/397861 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397861
TREATING SILICON NITRIDE BASED DIELECTRIC FILMS Dec 26, 2023 Pending
Array ( [id] => 20065645 [patent_doc_number] => 20250203867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => 3D NAND flash memory device and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 18/727085 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18727085 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/727085
Method of fabricating a 3D NAND flash memory with increased data retention capability Dec 10, 2023 Issued
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