Search

Gustavo G. Ramallo

Examiner (ID: 486, Phone: (571)272-9227 , Office: P/2819 )

Most Active Art Unit
2819
Art Unit(s)
2826, 2812, 2819
Total Applications
699
Issued Applications
602
Pending Applications
85
Abandoned Applications
28

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18823077 [patent_doc_number] => 20230397418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MICROELECTRONIC DEVICES INCLUDING IMPLANT REGIONS, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS [patent_app_type] => utility [patent_app_number] => 17/805167 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805167
Microelectronic devices including implant regions adjacent to dielectric slot structures, and related memory devices, electronic systems, and methods Jun 1, 2022 Issued
Array ( [id] => 17855486 [patent_doc_number] => 20220285529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => Dielectric Spacer to Prevent Contacting Shorting [patent_app_type] => utility [patent_app_number] => 17/664479 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664479
Dielectric spacer to prevent contacting shorting May 22, 2022 Issued
Array ( [id] => 17830365 [patent_doc_number] => 20220267669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => METHOD FOR MANUFACTURING PEROVSKITE NANOCRYSTAL PARTICLE LIGHT-EMITTER WHERE ORGANIC LIGAND IS SUBSTITUTED, NANOCRYSTAL PARTICLE LIGHT-EMITTER MANUFACTURED THEREBY, AND LIGHT EMITTING DEVICE USING SAME [patent_app_type] => utility [patent_app_number] => 17/740039 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17740039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/740039
Method for manufacturing perovskite nanocrystal particle light-emitter where organic ligand is substituted, nanocrystal particle light-emitter manufactured thereby, and light emitting device using same May 8, 2022 Issued
Array ( [id] => 19741393 [patent_doc_number] => 12218241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Semiconductor device structure with etch stop layer for reducing RC delay [patent_app_type] => utility [patent_app_number] => 17/705885 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 11916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705885 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705885
Semiconductor device structure with etch stop layer for reducing RC delay Mar 27, 2022 Issued
Array ( [id] => 20204187 [patent_doc_number] => 12406972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Stacked offset semiconductor package [patent_app_type] => utility [patent_app_number] => 17/699931 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3390 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699931 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699931
Stacked offset semiconductor package Mar 20, 2022 Issued
Array ( [id] => 18714784 [patent_doc_number] => 20230337428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/042754 [patent_app_country] => US [patent_app_date] => 2022-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -43 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18042754 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/042754
NOR-TYPE MEMORY DEVICE, METHOD OF MANUFACTURING NOR-TYPE MEMORY DEVICE, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE Feb 21, 2022 Pending
Array ( [id] => 19515843 [patent_doc_number] => 20240347529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => PROTECTION CIRCUIT AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/574986 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18574986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/574986
PROTECTION CIRCUIT AND SEMICONDUCTOR DEVICE Feb 14, 2022 Pending
Array ( [id] => 19200583 [patent_doc_number] => 11997847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Thin film transistors with spacer controlled gate length [patent_app_type] => utility [patent_app_number] => 17/588938 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10097 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588938
Thin film transistors with spacer controlled gate length Jan 30, 2022 Issued
Array ( [id] => 18047945 [patent_doc_number] => 11521903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Method of measuring voids in underfill package [patent_app_type] => utility [patent_app_number] => 17/564693 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4695 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564693 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564693
Method of measuring voids in underfill package Dec 28, 2021 Issued
Array ( [id] => 19110223 [patent_doc_number] => 11963356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Three-dimensional memory device without gate line slits and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/556745 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556745
Three-dimensional memory device without gate line slits and method for forming the same Dec 19, 2021 Issued
Array ( [id] => 18351235 [patent_doc_number] => 20230139346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => ADDITIONAL SILICIDE LAYER ON TOP OF STAIRCASE FOR 3D NAND WL CONTACT CONNECTION [patent_app_type] => utility [patent_app_number] => 17/549685 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549685 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549685
Additional silicide layer on top of staircase for 3D NAND WL contact connection Dec 12, 2021 Issued
Array ( [id] => 18346584 [patent_doc_number] => 20230134694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/457787 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457787
Three-dimensional memory device with charge trap layer including carbon region and fabrication method thereof Dec 5, 2021 Issued
Array ( [id] => 19245716 [patent_doc_number] => 12016180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Manufacturing method of three-dimensional memory device with improved RC delay [patent_app_type] => utility [patent_app_number] => 17/540190 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7512 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540190
Manufacturing method of three-dimensional memory device with improved RC delay Nov 30, 2021 Issued
Array ( [id] => 17949470 [patent_doc_number] => 20220336489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING SUPPORT STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/529331 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529331 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529331
Semiconductor device including support structure, method for manufacturing the same and electronic system including the same Nov 17, 2021 Issued
Array ( [id] => 19672843 [patent_doc_number] => 12185640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => MRAM MTJ with directly coupled top electrode connection [patent_app_type] => utility [patent_app_number] => 17/528574 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528574
MRAM MTJ with directly coupled top electrode connection Nov 16, 2021 Issued
Array ( [id] => 17389502 [patent_doc_number] => 20220037354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/451583 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451583
Method of forming a three-dimensional NAND memory device with reduced RC delay Oct 19, 2021 Issued
Array ( [id] => 19598531 [patent_doc_number] => 12156406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Methods of forming integrated assemblies with improved charge migration impedance [patent_app_type] => utility [patent_app_number] => 17/501951 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501951
Methods of forming integrated assemblies with improved charge migration impedance Oct 13, 2021 Issued
Array ( [id] => 19553834 [patent_doc_number] => 12137556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Method of manufacturing semiconductor device with improved gate insulation step [patent_app_type] => utility [patent_app_number] => 17/500297 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9329 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500297
Method of manufacturing semiconductor device with improved gate insulation step Oct 12, 2021 Issued
Array ( [id] => 17403008 [patent_doc_number] => 20220045099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => THREE-DIMENSIONAL FLASH MEMORY DEVICE WITH INCREASED STORAGE DENSITY [patent_app_type] => utility [patent_app_number] => 17/500370 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500370
Three-dimensional flash memory device with increased storage density Oct 12, 2021 Issued
Array ( [id] => 19681344 [patent_doc_number] => 12193233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Three-dimensional memory device with restrained charge migration and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/488915 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 9301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488915
Three-dimensional memory device with restrained charge migration and method for forming the same Sep 28, 2021 Issued
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