Search

Guy J. Lamarre

Examiner (ID: 8964)

Most Active Art Unit
2112
Art Unit(s)
2784, 2133, 2112
Total Applications
2026
Issued Applications
1799
Pending Applications
60
Abandoned Applications
172

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19616567 [patent_doc_number] => 20240402247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT [patent_app_type] => utility [patent_app_number] => 18/799555 [patent_app_country] => US [patent_app_date] => 2024-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18799555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/799555
Selectable JTAG or trace access with data store and output Aug 8, 2024 Issued
Array ( [id] => 19841526 [patent_doc_number] => 12253913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Memory error tracking and logging [patent_app_type] => utility [patent_app_number] => 18/438802 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 12505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438802 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438802
Memory error tracking and logging Feb 11, 2024 Issued
Array ( [id] => 19204647 [patent_doc_number] => 20240176546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => QUASI-VOLATILE MEMORY DEVICE WITH A BACK-CHANNEL USAGE [patent_app_type] => utility [patent_app_number] => 18/432930 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -39 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432930 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432930
Quasi-volatile memory device with a back-channel usage Feb 4, 2024 Issued
Array ( [id] => 19159717 [patent_doc_number] => 20240152424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => BLOCK FAILURE PROTECTION FOR ZONE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/406894 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406894 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406894
Block failure protection for zone memory system Jan 7, 2024 Issued
Array ( [id] => 19887455 [patent_doc_number] => 12273191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Bit order of NR PBCH payload to enhance polar code performance [patent_app_type] => utility [patent_app_number] => 18/395536 [patent_app_country] => US [patent_app_date] => 2023-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8634 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395536
Bit order of NR PBCH payload to enhance polar code performance Dec 22, 2023 Issued
Array ( [id] => 19669374 [patent_doc_number] => 12182121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Generating different segment groups for storage via storage devices of different storage clusters [patent_app_type] => utility [patent_app_number] => 18/543867 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 40 [patent_no_of_words] => 12458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/543867
Generating different segment groups for storage via storage devices of different storage clusters Dec 17, 2023 Issued
Array ( [id] => 19303426 [patent_doc_number] => 20240232006 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => MEMORY MANAGEMENT METHOD FOR SECURITY AND ELECTRONIC DEVICE THEREFOR [patent_app_type] => utility [patent_app_number] => 18/533281 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533281
Memory management method for security and electronic device therefor Dec 7, 2023 Issued
Array ( [id] => 19303426 [patent_doc_number] => 20240232006 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => MEMORY MANAGEMENT METHOD FOR SECURITY AND ELECTRONIC DEVICE THEREFOR [patent_app_type] => utility [patent_app_number] => 18/533281 [patent_app_country] => US [patent_app_date] => 2023-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533281
Memory management method for security and electronic device therefor Dec 7, 2023 Issued
Array ( [id] => 19766463 [patent_doc_number] => 12224771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Data reliability for extreme temperature usage conditions in data storage [patent_app_type] => utility [patent_app_number] => 18/513278 [patent_app_country] => US [patent_app_date] => 2023-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513278
Data reliability for extreme temperature usage conditions in data storage Nov 16, 2023 Issued
Array ( [id] => 18989777 [patent_doc_number] => 20240061746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => CONTROLLER CONTROLLING NON-VOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/501689 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18501689 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/501689
Controller controlling non-volatile memory device, storage device including the same, and operating method thereof Nov 2, 2023 Issued
Array ( [id] => 19419970 [patent_doc_number] => 20240296093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => ERROR CORRECTION DECODER, STORAGE DEVICE INCLUDING ERROR CORRECTION DECODER, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/498047 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18498047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/498047
Error correction decoder, storage device including error correction decoder, and operating method thereof Oct 30, 2023 Issued
Array ( [id] => 19734332 [patent_doc_number] => 12212340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Concatenated polar code with adaptive error detection [patent_app_type] => utility [patent_app_number] => 18/485381 [patent_app_country] => US [patent_app_date] => 2023-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 10050 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/485381
Concatenated polar code with adaptive error detection Oct 11, 2023 Issued
Array ( [id] => 18959945 [patent_doc_number] => 20240048272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => HARQ FOR ADVANCED CHANNEL CODES [patent_app_type] => utility [patent_app_number] => 18/483202 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483202
Harq for advanced channel codes Oct 8, 2023 Issued
Array ( [id] => 19538151 [patent_doc_number] => 12130704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Encoding and encrypting data in a storage network [patent_app_type] => utility [patent_app_number] => 18/479236 [patent_app_country] => US [patent_app_date] => 2023-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18479236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/479236
Encoding and encrypting data in a storage network Oct 1, 2023 Issued
Array ( [id] => 19036453 [patent_doc_number] => 20240086268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => METHOD FOR DECREASING PROBABILITY OF UNDETECTED ERRORS ON LARGE MESSAGES OVER A BLACK CHANNEL [patent_app_type] => utility [patent_app_number] => 18/367840 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18367840 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/367840
Method for decreasing probability of undetected errors on large messages over a black channel Sep 12, 2023 Issued
Array ( [id] => 18788035 [patent_doc_number] => 20230376432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMATION AND RELATED COMPUTING SYSTEMS, METHODS, AND APPARATUSES [patent_app_type] => utility [patent_app_number] => 18/365794 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365794 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365794
Separate inter-die connectors for data and error correction information and related computing systems, methods, and apparatuses Aug 3, 2023 Issued
Array ( [id] => 19779970 [patent_doc_number] => 12229003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Memory error detection and correction [patent_app_type] => utility [patent_app_number] => 18/230619 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8122 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230619
Memory error detection and correction Aug 3, 2023 Issued
Array ( [id] => 19538150 [patent_doc_number] => 12130703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Memory component with error-detect-correct code interface [patent_app_type] => utility [patent_app_number] => 18/230403 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230403 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230403
Memory component with error-detect-correct code interface Aug 3, 2023 Issued
Array ( [id] => 18925450 [patent_doc_number] => 20240028454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => INTERNAL ERROR CORRECTION FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/229547 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229547 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229547
Internal error correction for memory devices Aug 1, 2023 Issued
Array ( [id] => 19375328 [patent_doc_number] => 12066893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 18/226622 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 16385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18226622 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/226622
Semiconductor memory devices Jul 25, 2023 Issued
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