Search

Guy J. Lamarre

Examiner (ID: 2853, Phone: (571)272-3826 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2133, 2784, 2112
Total Applications
2026
Issued Applications
1799
Pending Applications
60
Abandoned Applications
172

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17283084 [patent_doc_number] => 11200113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Auto-increment write count for nonvolatile memory [patent_app_type] => utility [patent_app_number] => 16/742332 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16742332 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/742332
Auto-increment write count for nonvolatile memory Jan 13, 2020 Issued
Array ( [id] => 15908061 [patent_doc_number] => 20200153551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SYSTEMS AND METHODS FOR MITIGATING DECODING ERRORS DUE TO PUNCTURING OF SYMBOLS [patent_app_type] => utility [patent_app_number] => 16/733066 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/733066
Systems and methods for mitigating decoding errors due to puncturing of symbols Jan 1, 2020 Issued
Array ( [id] => 16559158 [patent_doc_number] => 20210004307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => OBTAINING OF STATISTICAL PERFORMANCE OF STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/731924 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731924
Obtaining of statistical performance of storage system Dec 30, 2019 Issued
Array ( [id] => 17046565 [patent_doc_number] => 11099745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/724278 [patent_app_country] => US [patent_app_date] => 2019-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 17605 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724278
Storage device and operating method thereof Dec 20, 2019 Issued
Array ( [id] => 15769075 [patent_doc_number] => 20200115555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Transformation of Binary Data to Non-Binary Data For Storage in Non-Volatile Memory [patent_app_type] => utility [patent_app_number] => 16/714601 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16714601 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/714601
Transformation of binary data to non-binary data for storage in non-volatile memory Dec 12, 2019 Issued
Array ( [id] => 16887363 [patent_doc_number] => 20210173560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => NON-VOLATILE MEMORY WITH ON-CHIP PRINCIPAL COMPONENT ANALYSIS FOR GENERATING LOW DIMENSIONAL OUTPUTS FOR MACHINE LEARNING [patent_app_type] => utility [patent_app_number] => 16/706618 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706618 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/706618
Non-volatile memory with on-chip principal component analysis for generating low dimensional outputs for machine learning Dec 5, 2019 Issued
Array ( [id] => 15685397 [patent_doc_number] => 20200097362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => METHODS AND APPARATUS FOR REDUCING MICROBUMPS FOR INTER-DIE DOUBLE-DATA RATE (DDR) TRANSFER [patent_app_type] => utility [patent_app_number] => 16/699225 [patent_app_country] => US [patent_app_date] => 2019-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699225 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699225
METHODS AND APPARATUS FOR REDUCING MICROBUMPS FOR INTER-DIE DOUBLE-DATA RATE (DDR) TRANSFER Nov 28, 2019 Abandoned
Array ( [id] => 15689613 [patent_doc_number] => 20200099470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => MANAGING INTEGRITY OF FRAMED PAYLOADS USING REDUNDANT SIGNALS [patent_app_type] => utility [patent_app_number] => 16/698126 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698126 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698126
Managing integrity of framed payloads using redundant signals Nov 26, 2019 Issued
Array ( [id] => 16819682 [patent_doc_number] => 11004519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/696508 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696508 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696508
Storage device and operating method thereof Nov 25, 2019 Issued
Array ( [id] => 16509930 [patent_doc_number] => 20200389186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => ERROR CORRECTION DECODER AND MEMORY SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 16/694929 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694929 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694929
Error correction decoder and memory system having the same Nov 24, 2019 Issued
Array ( [id] => 16273069 [patent_doc_number] => 20200274557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => METHOD OF VITERBI ALGORITHM AND RECEIVING DEVICE [patent_app_type] => utility [patent_app_number] => 16/691624 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691624 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/691624
Method of Viterbi algorithm and receiving device Nov 21, 2019 Issued
Array ( [id] => 17048626 [patent_doc_number] => 11101821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Method and device for incremental redundancy hybrid automatic repeat request (IR-HARQ) re-transmission [patent_app_type] => utility [patent_app_number] => 16/673421 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 5584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673421 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/673421
Method and device for incremental redundancy hybrid automatic repeat request (IR-HARQ) re-transmission Nov 3, 2019 Issued
Array ( [id] => 15594439 [patent_doc_number] => 20200073754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => ERROR CORRECTION CODE EVENT DETECTION [patent_app_type] => utility [patent_app_number] => 16/669343 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669343 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669343
Error correction code event detection Oct 29, 2019 Issued
Array ( [id] => 16795227 [patent_doc_number] => 20210125044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SUPPORT FOR DIFFERENT MATRIX MULTIPLICATIONS BY SELECTING ADDER TREE INTERMEDIATE RESULTS [patent_app_type] => utility [patent_app_number] => 16/667700 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667700
Support for different matrix multiplications by selecting adder tree intermediate results Oct 28, 2019 Issued
Array ( [id] => 16794826 [patent_doc_number] => 20210124643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => SELECTIVELY STORING PARITY DATA IN DIFFERENT TYPES OF MEMORY [patent_app_type] => utility [patent_app_number] => 16/663196 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/663196
Selectively storing parity data in different types of memory Oct 23, 2019 Issued
Array ( [id] => 15463711 [patent_doc_number] => 20200044680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => Systems and Methods for Die-to-Die Communication [patent_app_type] => utility [patent_app_number] => 16/600639 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16600639 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/600639
Systems and methods for die-to-die communication Oct 13, 2019 Issued
Array ( [id] => 17288285 [patent_doc_number] => 11204835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Error correcting memory systems [patent_app_type] => utility [patent_app_number] => 17/284642 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 20241 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17284642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/284642
Error correcting memory systems Oct 10, 2019 Issued
Array ( [id] => 16750988 [patent_doc_number] => 20210102997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => NON-VOLATILE COMPUTER DATA STORAGE PRODUCTION-LEVEL PROGRAMMING [patent_app_type] => utility [patent_app_number] => 16/592053 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/592053
Non-volatile computer data storage production-level programming Oct 2, 2019 Issued
Array ( [id] => 16729801 [patent_doc_number] => 20210096948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => UNCORRECTABLE ERROR CORRECTION CODE (UECC) RECOVERY TIME IMPROVEMENT [patent_app_type] => utility [patent_app_number] => 16/585503 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585503
Uncorrectable error correction code (UECC) recovery time improvement Sep 26, 2019 Issued
Array ( [id] => 16667174 [patent_doc_number] => 10936420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => RAID storage-device-assisted deferred Q data determination system [patent_app_type] => utility [patent_app_number] => 16/586530 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 12185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 503 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586530 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586530
RAID storage-device-assisted deferred Q data determination system Sep 26, 2019 Issued
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