Search

Guy J. Lamarre

Examiner (ID: 2853, Phone: (571)272-3826 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2133, 2784, 2112
Total Applications
2026
Issued Applications
1799
Pending Applications
60
Abandoned Applications
172

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16788039 [patent_doc_number] => 10990472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Spare substitution in memory system [patent_app_type] => utility [patent_app_number] => 16/516916 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 19167 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516916
Spare substitution in memory system Jul 18, 2019 Issued
Array ( [id] => 16462815 [patent_doc_number] => 10846163 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-24 [patent_title] => Hybrid hardware and software reporting management [patent_app_type] => utility [patent_app_number] => 16/517125 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 14145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517125
Hybrid hardware and software reporting management Jul 18, 2019 Issued
Array ( [id] => 19460657 [patent_doc_number] => 12101177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Terminal and radio communication method [patent_app_type] => utility [patent_app_number] => 17/626724 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 19346 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/626724
Terminal and radio communication method Jul 18, 2019 Issued
Array ( [id] => 16866522 [patent_doc_number] => 11025282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Transmitter and repetition method thereof [patent_app_type] => utility [patent_app_number] => 16/503945 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 30999 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503945 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503945
Transmitter and repetition method thereof Jul 4, 2019 Issued
Array ( [id] => 15349333 [patent_doc_number] => 20200012558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => Method of Parity Training for a DRAM Supporting a Link Error Checking and Correcting Functionality [patent_app_type] => utility [patent_app_number] => 16/459621 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16459621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/459621
Method of parity training for a DRAM supporting a link error checking and correcting functionality Jul 1, 2019 Issued
Array ( [id] => 16077535 [patent_doc_number] => 20200192754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => ERROR CORRECTION CODE CIRCUITS, SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/441287 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16441287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/441287
Error correction code circuits, semiconductor memory devices and memory systems Jun 13, 2019 Issued
Array ( [id] => 16638592 [patent_doc_number] => 10917114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Data transmission method, sending device, receiving device, and communications system [patent_app_type] => utility [patent_app_number] => 16/433985 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 12643 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16433985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/433985
Data transmission method, sending device, receiving device, and communications system Jun 5, 2019 Issued
Array ( [id] => 16895025 [patent_doc_number] => 11036579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Decoder for memory system and method thereof [patent_app_type] => utility [patent_app_number] => 16/432305 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6484 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432305
Decoder for memory system and method thereof Jun 4, 2019 Issued
Array ( [id] => 15257795 [patent_doc_number] => 20190377631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => VARIABLE RESISTANCE RANDOM-ACCESS MEMORY AND METHOD FOR WRITE OPERATION HAVING ERROR BIT RECOVERING FUNCTION THEREOF [patent_app_type] => utility [patent_app_number] => 16/431739 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/431739
Variable resistance random-access memory and method for write operation having error bit recovering function thereof Jun 4, 2019 Issued
Array ( [id] => 16488522 [patent_doc_number] => 20200382135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => FAULT-TOLERANT ANALOG COMPUTING [patent_app_type] => utility [patent_app_number] => 16/429983 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429983 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/429983
Fault-tolerant analog computing Jun 2, 2019 Issued
Array ( [id] => 16567403 [patent_doc_number] => 10892784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Memory device with enhanced error correction via data rearrangement, data partitioning, and content aware decoding [patent_app_type] => utility [patent_app_number] => 16/430380 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 10480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430380
Memory device with enhanced error correction via data rearrangement, data partitioning, and content aware decoding Jun 2, 2019 Issued
Array ( [id] => 16294234 [patent_doc_number] => 10771092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Method and apparatus for low density parity check channel coding in wireless communication system [patent_app_type] => utility [patent_app_number] => 16/423175 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 25541 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423175 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/423175
Method and apparatus for low density parity check channel coding in wireless communication system May 27, 2019 Issued
Array ( [id] => 16373162 [patent_doc_number] => 10804936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 64-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 16/393788 [patent_app_country] => US [patent_app_date] => 2019-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6566 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16393788 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/393788
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 64-symbol mapping, and bit interleaving method using same Apr 23, 2019 Issued
Array ( [id] => 14754437 [patent_doc_number] => 20190260392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => COMMUNCIATION METHOD USING POLAR CODE, AND WIRELESS DEVICE [patent_app_type] => utility [patent_app_number] => 16/391327 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16391327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/391327
Communication method using polar code, and wireless device Apr 22, 2019 Issued
Array ( [id] => 15027683 [patent_doc_number] => 20190324846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => Fault Tolerant Charge Parity Qubit [patent_app_type] => utility [patent_app_number] => 16/387931 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387931 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/387931
Fault tolerant charge parity qubit Apr 17, 2019 Issued
Array ( [id] => 14693077 [patent_doc_number] => 20190245654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => HIGH PERFORMANCE, FLEXIBLE, AND COMPACT LOW-DENSITY PARITY-CHECK (LDPC) CODE [patent_app_type] => utility [patent_app_number] => 16/387130 [patent_app_country] => US [patent_app_date] => 2019-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387130 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/387130
High performance, flexible, and compact low-density parity-check (LDPC) code Apr 16, 2019 Issued
Array ( [id] => 16494376 [patent_doc_number] => 10860418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => System and method for protecting GPU memory instructions against faults [patent_app_type] => utility [patent_app_number] => 16/378287 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7029 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378287
System and method for protecting GPU memory instructions against faults Apr 7, 2019 Issued
Array ( [id] => 15956935 [patent_doc_number] => 10666388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Encoder signal processing device and encoder [patent_app_type] => utility [patent_app_number] => 16/361415 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6733 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16361415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/361415
Encoder signal processing device and encoder Mar 21, 2019 Issued
Array ( [id] => 16700617 [patent_doc_number] => 10951237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Composing array codes for power of two and variable block sizes [patent_app_type] => utility [patent_app_number] => 16/362468 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362468
Composing array codes for power of two and variable block sizes Mar 21, 2019 Issued
Array ( [id] => 14511635 [patent_doc_number] => 20190199472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => TRANSMITTER AND SIGNAL PROCESSING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/293162 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16293162 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/293162
Transmitter and signal processing method thereof Mar 4, 2019 Issued
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